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? 1998 microchip technology inc. preliminary ds39016a-page 1 m devices included: microcontroller core features: high-performance risc cpu only 35 single word instructions to learn all single cycle instructions except for program branches which are two cycle operating speed: dc - 20 mhz clock input dc - 200 ns instruction cycle 2k x 14 words of program memory, 128 x 8 bytes of data memory (ram) interrupt capability eight level deep hardware stack direct, indirect, and relative addressing modes power-on reset (por) power-up timer (pwrt) and oscillator start-up timer (ost) watchdog timer (wdt) with its own on-chip rc oscillator for reliable operation programmable code-protection power saving sleep mode selectable oscillator options low-power, high-speed cmos technology fully static design wide operating voltage range: - 2.5v to 6.0v (pic16c72) - 2.5v to 5.5v (pic16cr72) high sink/source current 25/25 ma commercial, industrial and extended temperature ranges low-power consumption: - < 2 ma @ 5v, 4 mhz - 15 m a typical @ 3v, 32 khz - < 1 m a typical standby current pin diagrams peripheral features: timer0: 8-bit timer/counter with 8-bit prescaler timer1: 16-bit timer/counter with prescaler, can be incremented during sleep via external crystal/clock timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler capture, compare, pwm (ccp) module - capture is 16-bit, max. resolution is 12.5 ns - compare is 16-bit, max. resolution is 200 ns - pwm max. resolution is 10-bit 8-bit 5-channel analog-to-digital converter synchronous serial port (ssp) with spi ? and i 2 c ? brown-out detection circuitry for brown-out reset (bor) pic16c72 pic16cr72 pic16c72 mclr /v pp ra0/an0 ra1/an1 ra2/an2 ra3/an3/v ref ra4/t0cki ra5/ss /an4 v ss osc1/clkin osc2/clkout rc0/t1oso/t1cki rc1/t1osi rc2/ccp1 rc3/sck/scl rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0/int v dd v ss rc7 rc6 rc5/sdo rc4/sdi/sda ?1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 sdip, soic, ssop, pic16cr72 windowed side brazed ceramic pic16c72 series 8-bit cmos microcontrollers with a/d converter
pic16c72 series ds39016a -page 2 preliminary ? 1998 microchip technology inc. t ab le of contents 1.0 device overview ............................................................................................................................... ........................................... 3 2.0 memory organization ............................................................................................................................... .................................... 5 3.0 i/o ports ............................................................................................................................... ...................................................... 19 4.0 timer0 module ............................................................................................................................... ............................................ 25 5.0 timer1 module ............................................................................................................................... ............................................ 27 6.0 timer2 module ............................................................................................................................... ............................................ 31 7.0 capture/compare/pwm (ccp) module ............................................................................................................................... ...... 33 8.0 synchronous serial port (ssp) module ............................................................................................................................... ...... 39 9.0 analog-to-digital converter (a/d) module ............................................................................................................................... ... 53 10.0 special features of the cpu ............................................................................................................................... ....................... 59 11.0 instruction set summary ............................................................................................................................... ............................. 73 12.0 development support ............................................................................................................................... .................................. 75 13.0 electrical characteristics - pic16c72 series ............................................................................................................................. 77 14.0 dc and ac characteristics graphs and tables - pic16c72 ..................................................................................................... 97 15.0 dc and ac characteristics graphs and tables - pic16cr72 ................................................................................................ 107 16.0 packaging information ............................................................................................................................... ............................... 109 appendix a: what? new in this data sheet ............................................................................................................................... ... 115 appendix b: what? changed in this data sheet ........................................................................................................................... 115 appendix c: device differences ............................................................................................................................... ...................... 115 index ............................................................................................................................... ................................................................... 117 on-line support ............................................................................................................................... .................................................. 121 reader response ............................................................................................................................... ............................................... 122 pic16c72 series product identification system ............................................................................................................................... . 125 sales and support ............................................................................................................................... ............................................... 125 t o our v alued customers w e constantly str iv e to impro v e the quality of all our products and documentation. w e ha v e spent an e xceptional amount of time to ensure that these documents are correct. ho w e v er , w e realiz e that w e ma y ha v e missed a f e w things . if y ou nd an y inf or mation that is missing or appears in error , please use the reader response f or m in the bac k of this data sheet to inf or m us . w e appreciate y our assistance in making this a better document. k e y ref erence man ual features pic16c72 pic16cr72 o per ating f req uency dc - 2 0mhz dc - 20mhz resets por, pwr t , ost , bor por, pwr t , ost , bor prog r am memor y - (1 4 -bit w ords) 2k (epr om) 2k (r om) data memor y - ram ( 8-bit b ytes) 128 128 interr upts 8 8 i/o p or ts p or ta, p or tb , p or tc p or ta, p or tb , p or tc timers timer0, timer1, timer2 timer0, timer1, timer2 capture/compare/pwm modules 1 1 ser ial comm unications basic ssp ssp 8-bit a/d con v er ter 5 channels 5 channels instr uction set (no . of instr uctions) 35 35
pic16c72 series ? 1998 microchip technology inc. preliminary ds39016a -page 3 1.0 de vice over vie w this document contains de vice-speci c inf or mation f or the oper ation of the pic16c72 de vice . a dditional inf or- mation ma y be f ound in the picmicro mid -r ange mcu ref erence man ual (ds33023) which ma y be do wnloaded from the microchip w ebsite . t he ref er- ence man ual should be considered a complementar y document to this data sheet, and is highly recom- mended reading f or a better understanding of the de vice architecture and oper ation of the per ipher al modules . the pic16c72 belongs to the mid -r ange f amily of the picmicro de vices . a b loc k diag r am of the de vice is sho wn in figure 1-1 . the prog r am memor y contains 2k w ords which tr ans- late to 2048 instr uctions , since each 14-bit prog r am memor y w ord is the same width as each de vice instr uc- tion. t he data memor y (ram) contains 128 b ytes . there are also 22 i/o pins that are user-con gur ab le on a pin-to-pin basis . s ome pins are m ultiple x ed with other de vice functions . t hese functions include: exter nal interr upt change on por tb interr upt timer0 cloc k input timer1 cloc k/oscillator capture/compare/pwm a/d con v er ter spi/i 2 c t ab le 1-1 details the pinout of the de vice with descr ip- tions and details f or each pin. figure 1-1: pic16c72/cr72 blo c k dia g ram epr om / prog r am memor y 2k x 14 13 data bus 8 14 prog r am bus instr uction reg prog r am counter 8 le v el stac k (13-bit) ram file registers 128 x 8 direct addr 7 ram addr (1) 9 addr mux indirect addr fsr reg st a tus reg mux alu w reg p o w er-up timer oscillator star t-up timer p o w er-on reset w atchdog timer instr uction decode & control timing gener ation osc1/clkin osc2/clk out mclr v dd , v ss timer0 a/d synchronous ser ial p or t por t a por tb por tc rb0/int rb7:rb1 rc0/t1oso/t1cki rc1/t1osi rc2/ccp1 rc3/sck/scl rc4/sdi/sd a rc5/sdo rc6 rc7 8 8 bro wn-out reset note 1: higher order bits are from the st a tus register . ccp1 timer1 timer2 ra4/t0cki ra5 / ss /an4 ra3/an3/ v ref ra2/an2 ra1/an1 ra0/an0 8 3 r om
pic16c72 series ds39016a -page 4 preliminary ? 1998 microchip technology inc. t able 1-1 pic16c72/cr72 pinout description pin name pin# i/o/p t ype buff er t ype description osc1/clkin 9 i st/cmos (3) oscillator cr ystal input/e xter nal cloc k source input. osc2/clk out 10 o oscillator cr ystal output. connects to cr ystal or resonator in cr ystal oscillator mode . in rc mode , the osc2 pin outputs clk out which has 1/4 the frequency of osc1, and denotes the instr uction cycle r ate . mclr / v pp 1 i/p st master clear (reset) input or prog r amming v oltage input. this pin is an activ e lo w reset to the de vice . por t a is a bi-directional i/o por t. ra0/an0 2 i/o ttl ra0 can also be analog input0. ra1/an1 3 i/o ttl ra1 can also be analog input1. ra2/an2 4 i/o ttl ra2 can also be analog input2. ra3/an3/ v ref 5 i/o ttl ra3 can also be analog input3 or analog ref erence v oltage ra4/t0cki 6 i/o st ra4 can also be the cloc k input to the timer0 module . output is open dr ain type . ra5/ ss/an4 7 i/o ttl ra5 can also be analog input4 or the sla v e select f or the synchronous ser ial por t. por tb is a bi-directional i/o por t. por tb can be softw are prog r ammed f or inter nal w eak pull-up on all inputs . rb0/int 21 i/o ttl/st (1) rb0 can also be the e xter nal interr upt pin. rb1 22 i/o ttl rb2 23 i/o ttl rb3 24 i/o ttl rb4 25 i/o ttl interr upt on change pin. rb5 26 i/o ttl interr upt on change pin. rb6 27 i/o ttl/st (2) interr upt on change pin. ser ial prog r amming cloc k. rb7 28 i/o ttl/st (2) interr upt on change pin. ser ial prog r amming data. por tc is a bi-directional i/o por t. rc0/t1oso/t1cki 11 i/o st rc0 can also be the timer1 oscillator output or timer1 cloc k input. rc1/t1osi 12 i/o st rc1 can also be the timer1 oscillator input. rc2/ccp1 13 i/o st rc2 can also be the capture1 input/compare1 output/pwm1 output. rc3/sck/scl 14 i/o st rc3 can also be the synchronous ser ial cloc k input/output f or both spi and i 2 c modes . rc4/sdi/sd a 15 i/o st rc4 can also be the spi data in (spi mode) or data i/o (i 2 c mode). rc5/sdo 16 i/o st rc5 can also be the spi data out (spi mode). rc6 17 i/o st rc7 18 i/o st v ss 8, 19 p ground ref erence f or logic and i/o pins . v dd 20 p p ositiv e supply f or logic and i/o pins . legend: i = input o = output i/o = input/output p = po w er ?= not used ttl = ttl input st = schmitt t r igger input note 1: this b uff er is a schmitt t r igger input when con gured as the e xter nal interr upt. 2: this b uff er is a schmitt t r igger input when used in ser ial prog r amming mode . 3: this b uff er is a schmitt t r igger input when con gured in rc oscillator mode and a cmos input otherwise .
pic16c72 series ? 1998 microchip technology inc. preliminary ds39016a -page 5 2.0 memor y or ganization there are tw o memor y b loc ks in pic16c72 ser ies de vices . these are the prog r am memor y and the data memor y . each b loc k has its o wn b us , so that access to both b loc k s can occur dur ing the same oscillator cycle . the data memor y can fur ther be brok en do wn into the gener al pur pose ram and the special function registers (sfrs). the oper ation of the sfrs that control the ?ore are descr ibed here . the sfrs used to control the per ipher al modules are descr ibed in the section discussing each individual per ipher al module . additional inf or mation on de vice memor y ma y be f ound in the picmicro mid-range ref erence man ual, ds33023. 2.1 pr ogram memor y or ganization pic16c72 ser ies de vices ha v e a 13-bit prog r am counter capab le of addressing a 2k x 14 prog r am memor y space . the address r ange f or this prog r am memor y is 0000h - 07ffh. accessing a location abo v e the ph ysically implemented address will cause a wr ap- around. the reset v ector is at 0000h and the interr upt v ector is at 0004h. figure 2-1: pr ogram memor y map and stac k pc<12:0> 13 0000h 0004h 0005h 07ffh 1fffh stac k le v el 1 stac k le v el 8 reset v ector interr upt v ector on-chip prog r am memor y call, return retfie, retlw 0800h user memor y space
pic16c72 series ds39016a -page 6 preliminary ? 1998 microchip technology inc. 2.2 data memor y or ganization the data memor y is par titioned into m ultiple banks which contain the gener al pur pose registers and the special function registers . bits rp1 and rp0 are the bank select bits . = 00 ? bank0 = 01 ? bank1 = 10 ? bank2 (not implemented) = 11 ? bank3 (not implemented) each bank e xtends up to 7fh (128 b ytes). the lo w er locations of each bank are reser v ed f or the special function registers . abo v e the special function regis- ters are gener al pur pose registers , implemented as static ram. all implemented banks contain special function regis- ters . some ?igh use special function registers from one bank ma y be mirrored in another bank f or code reduction and quic k er access (e x; the st a tus register is in bank 0 and bank 1). 2.2.1 gener al pur pose register file the register le can be accessed either directly or indi- rectly through the file select register fsr ( section 2.5 ). figure 2-2: re gister file map rp1* rp0 (st a tus<6:5>) * maintain this bit clear to ensure upw ard com- patibility with future products . indf (1) tmr0 pcl st a tus fsr por t a por tb por tc pcla th intcon pir1 tmr1l tmr1h t1con tmr2 t2con sspb uf sspcon ccpr1l ccpr1h ccp1con adres adcon0 indf (1) option pcl st a tus fsr trisa trisb trisc pcla th intcon pie1 pcon pr2 ssp add sspst a t adcon1 00 h 01 h 02 h 03 h 04 h 05 h 06 h 07 h 08 h 09 h 0a h 0b h 0c h 0d h 0e h 0f h 10 h 11 h 12 h 13 h 14 h 15 h 16 h 17 h 18 h 19 h 1a h 1b h 1c h 1d h 1e h 1 fh 80 h 81 h 82 h 83 h 84 h 85 h 86 h 87 h 88 h 89 h 8a h 8b h 8c h 8d h 8e h 8f h 90 h 91 h 92 h 93 h 94 h 95 h 96 h 97 h 98 h 99 h 9a h 9b h 9c h 9d h 9e h 9f h 20 h a0 h gener al pur pose register gener al pur pose register 7f h ffh bank 0 bank 1 file address bfh c0 h unimplemented data memor y locations , read as '0'. note 1: not a ph ysical register . file address
pic16c72 series ? 1998 microchip technology inc. preliminary ds39016a -page 7 2.2.2 special function registers the special function registers are registers used b y the cpu and p er ipher al modules f or controlling the desired oper ation of the de vice . these registers are implemented as static ram. the special function registers can be classi ed into tw o sets (core and per ipher al). those registers associated with the ?ore functions are descr ibed in this section, and those related to the oper ation of the per ipher al f ea- tures are descr ibed in the section of that per ipher al f ea- ture . t able 2-1 special functio n register summar y ad dress name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 v alue on: por, bor v alue on all other resets (3) bank 0 00 h (1) indf addressing this location uses contents of fsr to address data memor y (not a ph ysical register) 0000 0000 0000 0000 01 h tmr0 timer0 module s register xxxx xxxx uuuu uuuu 02 h (1) pcl prog r am counter's (pc ) least signi cant byte 0000 0000 0000 0000 03 h (1) st a tus irp (4) rp1 (4) rp0 t o pd z dc c 0001 1xxx 000q quuu 04 h (1) fsr indirect data memor y address pointer xxxx xxxx uuuu uuuu 05 h por t a por t a data latch when wr itten: por t a pins when read --0x 0000 --0u 0000 06 h por tb por tb data latch when wr itten: por tb pins when read xxxx xxxx uuuu uuuu 07 h por tc por tc data latch when wr itten: por tc pins when read xxxx xxxx uuuu uuuu 08 h unimplemented 09 h unimplemented 0a h (1,2) pcla th wr ite buff er f or the upper 5 bits of the prog r am counter ---0 0000 ---0 0000 0b h (1) intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0c h pir1 adif sspif ccp1if tmr2if tmr1if -0-- 0000 -0-- 0000 0d h unimplemented 0e h tmr1l holding register f or the l east signi cant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 0f h tmr1h holding register f or the m ost signi cant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 10 h t1con t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on --00 0000 --uu uuuu 11 h tmr2 timer2 module s register 0000 0000 0000 0000 12 h t2con t outps3 t outps2 t outps1 t outps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 13 h sspb uf synchronous ser ial p or t receiv e buff er/t r ansmit register xxxx xxxx uuuu uuuu 14 h sspcon wcol sspo v sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 15 h ccpr1l capture/compare/ pwm r egister (lsb) xxxx xxxx uuuu uuuu 16 h ccpr1h capture/compare/ pwm r egister (msb) xxxx xxxx uuuu uuuu 17 h ccp1con ccp1x ccp1y ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 18 h -1dh unimplemented 1e h adres a/d result register xxxx xxxx uuuu uuuu 1f h adcon0 adcs1 adcs0 chs2 chs1 chs0 go/ done adon 0000 00-0 0000 00-0 legend: x = unkno wn, u = unchanged, q = v alue depends on condition, - = unimplemented read as '0'. shaded locations are unimplemented, read as ?? note 1: these registers can be addressed from either bank. 2: the upper b yte of the prog r am counter is not directly accessib le . pcla th is a holding register f or the pc<12:8> whose con- tents are tr ansf erred to the upper b yte of the prog r am counter . 3: other (non po w er-up) resets include e xter nal reset through mclr and w atchdog timer reset. 4: the irp and rp1 bits are reser v ed on the pic16c72/cr72. alw a ys maintain these bits clear . 5: sspst a t<7:6> are not implemented on the pic16c72, read as '0'.
pic16c72 series ds39016a -page 8 preliminary ? 1998 microchip technology inc. bank 1 80 h (1) indf addressing this location uses contents of fsr to address data memor y (not a ph ysical register) 0000 0000 0000 0000 81 h option_reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 82 h (1) pcl prog r am counter's (pc ) l east signi cant byte 0000 0000 0000 0000 83 h (1) st a tus irp (4) rp1 (4) rp0 t o pd z dc c 0001 1xxx 000q quuu 84 h (1) fsr indirect data memor y address pointer xxxx xxxx uuuu uuuu 85 h trisa por t a data direction register --11 1111 --11 1111 86 h trisb por tb data direction register 1111 1111 1111 1111 87 h trisc por tc data direction register 1111 1111 1111 1111 88 h unimplemented 89 h unimplemented 8a h (1,2) pcla th wr ite buff er f or the upper 5 bits of the pc ---0 0000 ---0 0000 8b h (1) intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 8c h pie1 adie sspie ccp1ie tmr2ie tmr1ie -0-- 0000 -0-- 0000 8d h unimplemented 8e h pcon por bo r ---- --qq ---- --uu 8f h unimplemented 90 h unimplemented 91 h unimplemented 92 h pr2 timer2 p er iod register 1111 1111 1111 1111 93 h ssp add synchronous ser ial p or t (i 2 c mode) address register 0000 0000 0000 0000 94 h sspst a t smp (5) cke (5) d/ a p s r/ w u a bf 000 0 0000 000 0 0000 95 h unimplemented 96 h unimplemented 97 h unimplemented 98 h unimplemented 99 h unimplemented 9a h unimplemented 9b h unimplemented 9c h unimplemented 9d h unimplemented 9e h unimplemented 9f h adcon1 pcfg2 pcfg1 pcfg0 ---- -000 ---- -000 t able 2-1 special functio n register summar y (contin ued) ad dress name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 v alue on: por, bor v alue on all other resets (3) legend: x = unkno wn, u = unchanged, q = v alue depends on condition, - = unimplemented read as '0'. shaded locations are unimplemented, read as ?? note 1: these registers can be addressed from either bank. 2: the upper b yte of the prog r am counter is not directly accessib le . pcla th is a holding register f or the pc<12:8> whose con- tents are tr ansf erred to the upper b yte of the prog r am counter . 3: other (non po w er-up) resets include e xter nal reset through mclr and w atchdog timer reset. 4: the irp and rp1 bits are reser v ed on the pic16c72/cr72. alw a ys maintain these bits clear . 5: sspst a t<7:6> are not implemented on the pic16c72, read as '0'.
pic16c72 series ? 1998 microchip technology inc. preliminary ds39016a -page 9 2.2.2.1 st a tus register the st a tus register , sho wn in figure 2-3 , contains the ar ithmetic status of the alu , the reset status and the bank select bits f or data memor y . the st a tus register can be the destination f or an y instr uction, as with an y other register . if the st a tus register is the destination f or an instr uction that aff ects the z, dc or c bits , then the wr ite to these three bits is disab led. these bits are set or cleared according to the de vice logic. fur ther more , the t o and pd bits are not wr itab le . theref ore , the result of an instr uction with the st a tus register as destination ma y be diff erent than intended. f or e xample , clrf status will clear the upper-three bits and set the z bit. this lea v es the st a tus register as 000u u1uu (where u = unchanged). it is recommended, theref ore , that only bcf, bsf, swapf and movwf instr uctions are used to alter the st a tus register because these instr uctions do not aff ect the z, c or dc bits from the st a tus register . f or other instr uctions , not aff ecting an y status bits , see the "instr uction set summar y ." figure 2-3: status r egi ster (ad dress 03 h , 83 h ) note 1: these de vices do not use bits irp and rp1 (st a tus<7:6>). maintain these bits clear to ensure u pw ard compatibility with future products . note 2: the c and dc bits oper ate as a borro w and digit borro w bit, respectiv ely , in sub- tr action. see the sublw and subwf instr uctions f or e xamples . r/w -0 r/w -0 r/w -0 r-1 r-1 r/w -x r/w -x r/w -x irp rp1 rp0 t o pd z dc c r = readab le bit w = wr itab le bit u = unimplemented bit, read as ? - n = v alue at por reset bit7 bit0 bit 7: irp : register bank select bit (used f or indirect addressing) 1 = bank 2, 3 (100h - 1ffh) 0 = bank 0, 1 (00h - ffh) bit 6-5: rp1:rp0 : register bank select bits (used f or direct addressing) 11 = bank 3 (180h - 1ffh) 10 = bank 2 (100h - 17fh) 01 = bank 1 (80h - ffh) 00 = bank 0 (00h - 7fh) each bank is 128 b ytes . f or de vices with only bank0 and bank1, the irp bit is reser v ed. a lw a ys maintain this bit clear . bit 4: t o : time-out bit 1 = after po w er-up , clrwdt instr uction, or sleep instr uction 0 = a wdt time-out occurred bit 3: pd : p o w er-do wn bit 1 = after po w er-up or b y the clrwdt instr uction 0 = by e x ecution of the sleep instr uction bit 2: z : zero bit 1 = the result of an ar ithmetic or logic oper ation is z ero 0 = the result of an ar ithmetic or logic oper ation is not z ero bit 1: dc : digit carr y/ borro w bit ( addwf , addlw,sublw,subwf instr uctions) (f or borro w the polar ity is re v ersed) 1 = a carr y-out from the 4th lo w order bit of the result occurred 0 = no carr y-out from the 4th lo w order bit of the result bit 0: c : carr y/ borro w bit ( addwf , addlw,sublw,subwf instr uctions) 1 = a carr y-out from the most signi cant bit of the result occurred 0 = no carr y-out from the most signi cant bit of the result occurred note: f or borro w the polar ity is re v ersed. a subtr action is e x ecuted b y adding the tw o s complement of the second oper and. f or rotate ( rrf , rlf ) instr uctions , this bit is loaded with either the high or lo w order bit of the source register .
pic16c72 series ds39016a -page 10 preliminary ? 1998 microchip technology inc. 2.2.2.2 option_reg register the option_reg register is a readab le and wr itab le register which contains v ar ious control bits to con gure the tmr0 prescaler/wdt postscaler (single assign- ab le register kno wn also as the prescaler), the exter nal int interr upt, tmr0, and the w eak pull-ups on por tb . figure 2-4: optio n_reg register (ad dress 81 h ) note: t o achie v e a 1:1 prescaler assignment f or the tmr0 register , assign the prescaler to the w atchdog timer . r/w -1 r/w -1 r/w -1 r/w -1 r/w -1 r/w -1 r/w -1 r/w -1 rbpu intedg t0cs t0se psa ps2 ps1 ps0 r = readab le bit w = wr itab le bit u = unimplemented bit, read as ? - n = v alue at por reset bit7 bit0 bit 7: rbpu : por tb pull-up enab le bit 1 = por tb pull-ups are disab led 0 = por tb pull-ups are enab led b y individual por t latch v alues bit 6: intedg : interr upt edge select bit 1 = interr upt on r ising edge of rb0/int pin 0 = interr upt on f alling edge of rb0/int pin bit 5: t0cs : tmr0 cloc k source select bit 1 = t r ansition on ra4/t0cki pin 0 = inter nal instr uction cycle cloc k (clk out) bit 4: t0se : tmr0 source edge select bit 1 = increment on high-to-lo w tr ansition on ra4/t0cki pin 0 = increment on lo w-to-high tr ansition on ra4/t0cki pin bit 3: psa : prescaler assignment bit 1 = prescaler is assigned to the wdt 0 = prescaler is assigned to the timer0 module bit 2-0: ps2:ps0 : prescaler rate select bits 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 bit v alue tmr0 rate wdt rate
pic16c72 series ? 1998 microchip technology inc. preliminary ds39016a -page 11 2.2.2.3 intcon register the intcon register is a readab le and wr itab le regis- ter which contains v ar ious enab le and ag bits f or the tmr0 register o v er o w , rb p or t change and exter nal rb0/int pin interr upts . figure 2-5: intcon register ( ad dress 0b h , 8b h ) note: interr upt ag bits get set when an interr upt condition occurs regardless of the state of its corresponding enab le bit or the global enab le bit, gie (intcon<7>). user soft- w are should ensure the appropr iate inter- r upt ag bits are clear pr ior to enab ling an interr upt. r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -x gie peie t0ie inte rbie t0if intf rbif r = readab le bit w = wr itab le bit u = unimplemented bit, read as ? - n = v alue at por reset bit7 bit0 bit 7: gie: global interr upt enab le bit 1 = enab les all un-mask ed interr upts 0 = disab les all interr upts bit 6: peie : p er ipher al interr upt enab le bit 1 = enab les all un-mask ed per ipher al interr upts 0 = disab les all per ipher al interr upts bit 5: t0ie : tmr0 ov er o w interr upt enab le bit 1 = enab les the tmr0 interr upt 0 = disab les the tmr0 interr upt bit 4: inte : rb0/int exter nal interr upt enab le bit 1 = enab les the rb0/int e xter nal interr upt 0 = disab les the rb0/int e xter nal interr upt bit 3: rbie : rb p or t change interr upt enab le bit 1 = enab les the rb por t change interr upt 0 = disab les the rb por t change interr upt bit 2: t0if : tmr0 ov er o w interr upt flag bit 1 = tmr0 register has o v er o w ed (m ust be cleared in softw are) 0 = tmr0 register did not o v er o w bit 1: intf : rb0/int exter nal interr upt flag bit 1 = the rb0/int e xter nal interr upt occurred (m ust be cleared in softw are) 0 = the rb0/int e xter nal interr upt did not occur bit 0: rbif : rb p or t change interr upt flag bit 1 = at least one of the rb7:rb4 pins changed state (m ust be cleared in softw are) 0 = none of the rb7:rb4 pins ha v e changed state
pic16c72 series ds39016a -page 12 preliminary ? 1998 microchip technology inc. 2.2.2.4 pie1 register this register contains the individual enab le bits f or the per ipher al interr upts . figure 2-6: pie1 registe r (ad dress 8c h ) note: bit peie (intcon<6>) m ust be set to enab le an y per ipher al interr upt. u-0 r/w -0 u-0 u-0 r/w -0 r/w -0 r/w -0 r/w -0 adie sspie ccp1ie tmr2ie tmr1ie r = readab le bit w = wr itab le bit u = unimplemented bit, read as ? - n = v alue at por reset bit7 bit0 bit 7: unimplemented: read as '0' bit 6: adie : a/d con v er ter interr upt enab le bit 1 = enab les the a/d interr upt 0 = disab les the a/d interr upt bit 5-4: unimplemented : read as '0' bit 3: sspie : synchronous ser ial p or t interr upt enab le bit 1 = enab les the ssp interr upt 0 = disab les the ssp interr upt bit 2: ccp1ie : ccp1 interr upt enab le bit 1 = enab les the ccp1 interr upt 0 = disab les the ccp1 interr upt bit 1: tmr2ie : tmr2 to pr2 match interr upt enab le bit 1 = enab les the tmr2 to pr2 match interr upt 0 = disab les the tmr2 to pr2 match interr upt bit 0: tmr1ie : tmr1 ov er o w interr upt enab le bit 1 = enab les the tmr1 o v er o w interr upt 0 = disab les the tmr1 o v er o w interr upt
pic16c72 series ? 1998 microchip technology inc. preliminary ds39016a -page 13 2.2.2.5 pir1 register this register contains the individual ag bits f or the p er ipher al interr upts . figure 2-7: pir1 registe r (ad dress 0c h ) note: interr upt ag bits get set when an interr upt condition occurs regardless of the state of its corresponding enab le bit or the global enab le bit, gie (intcon<7>). user soft- w are should ensure the appropr iate inter- r upt ag bits are clear pr ior to enab ling an interr upt. u-0 r/w -0 u-0 u-0 r/w -0 r/w -0 r/w -0 r/w -0 adif sspif ccp1if tmr2if tmr1if r = readab le bit w = wr itab le bit u = unimplemented bit, read as ? - n = v alue at por reset bit7 bit0 bit 7: unimplemented: read as '0' bit 6: adif : a/d con v er ter interr upt flag bit 1 = an a/d con v ersion completed (m ust be cleared in softw are) 0 = the a/d con v ersion is not complete bit 5-4: unimplemented : read as '0' bit 3: sspif : synchronous ser ial p or t interr upt flag bit 1 = the tr ansmission/reception is complete (m ust be cleared in softw are) 0 = w aiting to tr ansmit/receiv e bit 2: ccp1if : ccp1 interr upt flag bit capture mode 1 = a tmr1 register capture occurred (m ust be cleared in softw are) 0 = no tmr1 register capture occurred compare mode 1 = a tmr1 register compare match occurred (m ust be cleared in softw are) 0 = no tmr1 register compare match occurred pwm mode un used in this mode bit 1: tmr2if : tmr2 to pr2 match interr upt flag bit 1 = tmr2 to pr2 match occurred (m ust be cleared in softw are) 0 = no tmr2 to pr2 match occurred bit 0: tmr1if : tmr1 ov er o w interr upt flag bit 1 = tmr1 register o v er o w ed (m ust be cleared in softw are) 0 = tmr1 register did not o v er o w
pic16c72 series ds39016a -page 14 preliminary ? 1998 microchip technology inc. 2.2.2.6 pcon register the p o w er control (pcon) register contains a ag bit to allo w diff erentiation betw een a p o w er-on reset (por) to an e xter nal mclr reset or wdt reset. those de vices with bro wn-out detection circuitr y con- tain an additional bit to diff erentiate a bro wn-out reset condition from a p o w er-on reset condition. figure 2-8: pcon regi ster (ad dress 8e h ) note: bor is unkno wn on p o w er-on reset. it m ust then be set b y the user and chec k ed on subsequent resets to see if bor is clear , indicating a bro wn-out has occurred. the bor status bit is a don't care and is not necessar ily predictab le if the bro wn-out circuit is disab led (b y clear ing the boden bit in the con gur ation w ord). u-0 u-0 u-0 u-0 u-0 u-0 r/w -0 r/w -q por bor r = readab le bit w = wr itab le bit u = unimplemented bit, read as ? - n = v alue at por reset bit7 bit0 bit 7-2: unimplemented: read as '0' bit 1: por : p o w er-on reset status bit 1 = no p o w er-on reset occurred 0 = a p o w er-on reset occurred (m ust be set in softw are after a p o w er-on reset occurs) bit 0: bor : bro wn-out reset status bit 1 = no bro wn-out reset occurred 0 = a bro wn-out reset occurred (m ust be set in softw are after a bro wn-out reset occurs)
pic16c72 series ? 1998 microchip technology inc. preliminary ds39016a -page 15 2.3 pcl and pcla th the prog r am counter (pc) speci es the address of the instr uction to f etch f or e x ecution. the pc is 13 bits wide . the lo w b yte is called the pcl register . this reg- ister is readab le and wr itab le . the high b yte is called the pch register . this register contains the pc<12:8> bits and is not directly readab le or wr itab le . all updates to the pch register go through the pcla th register . figure 2-9 sho ws the f our situations f or the loading of the pc . example 1 sho ws ho w the pc is loaded on a wr ite to pcl (pcla th<4:0> ? pch). example 2 sho ws ho w the pc is loaded dur ing a goto instr uction (pcla th<4:3> ? pch). example 3 sho ws ho w the pc is loaded dur ing a call instr uction (pcla th<4:3> ? pch), with the pc loaded (pushed) onto the t op of stac k. finally , e xample 4 sho ws ho w the pc is loaded dur ing one of the retur n instr uctions where the pc is loaded (pop ed) from the t op of stac k. figure 2-9: loading of pc in diff erent situations pc 12 8 7 0 5 pcla th<4:0> pcla th alu result opcode <10:0> 8 pc 12 11 10 0 11 pcla th<4:3> pch pcl 8 7 2 pcla th pch pcl situation 1 - instruction with pcl as destination situation 2 - goto instruction st a ck (13-bits x 8) t op of st a ck st a ck (13-bits x 8) t op of st a ck opcode <10:0> pc 12 11 10 0 11 pcla th<4:3> 8 7 2 pcla th pch pcl situation 3 - call instruction st a ck (13-bits x 8) t op of st a ck opcode <10:0> pc 12 11 10 0 11 8 7 pcla th pch pcl situation 4 - return , retfie , or retlw instruction st a ck (13-bits x 8) t op of st a ck 13 13 note: pcla th is n ot u pdated with the contents of pch.
pic16c72 series ds39016a -page 16 preliminary ? 1998 microchip technology inc. 2.3.1 stac k the stac k allo ws a combination of up to 8 prog r am calls and interr upts to occur . the stac k contains the retur n address from this br anch in prog r am e x ecution. midr ange de vices ha v e an 8 le v el deep x 13-bit wide hardw are stac k. the stac k space is not par t of either prog r am or data space and the stac k pointer is not readab le or wr itab le . the pc is pushed onto the stac k when a call instr uction is e x ecuted or an interr upt causes a br anch. the stac k is pop ed in the e v ent of a return, retlw or a retfie instr uction e x ecution. pcla th is not modi ed when the stac k is pushed or pop ed. after the stac k has been pushed eight times , the ninth push o v erwr ites the v alue that w as stored from the rst push. the tenth push o v erwr ites the second push (and so on). an e xample of the o v erwr iting of the stac k is sho wn in figure 2-10 . figure 2-10: stac k modification 2.4 pr ogram memor y p a ging the call and goto instr uctions pro vide 11 bits of address to allo w br anching within an y 2k prog r am memor y page . when doing a call or goto instr uction the upper 2 bits of the address are pro vided b y pcla th<4:3>. when doing a call or goto instr uction, the user m ust ensure that the page select bits are pro- g r ammed so that the desired prog r am memor y page is addressed. if a retur n from a call instr uction (or inter- r upt) is e x ecuted, the entire 13-bit pc is pushed onto the stac k. theref ore , manipulation of the pcla th<4:3> bits are not required f or the retur n instr uctions (which pops the address from the stac k). push1 push9 push2 push10 push3 push4 push5 push6 push7 push8 t op of st a ck st a ck note: pic16c72 ser ies de vices ignore paging bit pcla th<4>. the use of p cla th<4> as a gener al pur pose read/wr ite bit is not recommended since this ma y aff ect upw ard compatibility with future products .
pic16c72 series ? 1998 microchip technology inc. preliminary ds39016a -page 17 2.5 indirect ad dressing, indf and fsr register s the indf register is not a ph ysical register . address- ing indf actually addresses the register whose address is contained in the fsr register ( fsr is a pointer ). this is indirect addressing. example 2-1: indirect ad dressing register le 05 contains the v alue 10h register le 06 contains the v alue 0ah load the v alue 05 into the fsr register a read of the indf register will retur n the v alue of 10h increment the v alue of the fsr register b y one (fsr = 06) a read of the indr register no w will retur n the v alue of 0ah. reading indf itself indirectly (fsr = 0) will produce 00h. wr iting to the indf register indirectly results in a no-oper ation (although st a tus bits ma y be aff ected). a simple prog r am to clear ram locations 20h-2fh using indirect addressing is sho wn in example 2-2 . example 2-2: ho w to clear ram using indirect ad dressing movlw 0 x20 ;initialize pointer movwf fsr ; to ram next clrf indf ;clear indf register incf fsr ;inc pointer btfss fsr,4 ;all done? goto next ;no, clear next continue : ;yes, continue an eff ectiv e 9-bit address is obtained b y concatenating the 8-bit fsr register and the irp bit (st a tus<7>), as sho wn in figure 2-11 . ho w e v er , irp is not used in the pic16c72 ser ies . figure 2-11: direct/indi rect ad dressing note 1: f or register le map detail see figure 2-2 . 2: maintain rp1 and irp as clear f or upw ard compatibility with future products . 3: not implemented. data memor y (1) indirect ad dressing direct ad dressing bank select location select rp1: rp0 6 0 from opcode irp fsr register 7 0 bank select location select 00 01 10 11 bank 0 bank 1 bank 2 bank 3 not used ffh 80 h 7fh 00h 1 7fh 1 00h 1ff h 180 h (2) (2) (3) (3)
pic16c72 series ds39016a -page 18 preliminary ? 1998 microchip technology inc. notes:
pic16c72 series ? 1998 microchip technology inc. preliminary ds39016a -page 19 3.0 i/o p or ts some pins f or these i/o por ts are m ultiple x ed with an alter nate function f or the per ipher al f eatures on the de vice . in gener al, when a per ipher al is enab led, that pin ma y not be used as a gener al pur pose i/o pin. additional inf or mation on i/o por ts ma y be f ound in the picmicro mid-range mcu ref erence man ual, ds33023. 3.1 por t a and the trisa register por t a is a 6-bit wide bi-directional por t. the corre- sponding data direction register is trisa. setting a trisa bit (=1) will mak e the corresponding por t a pin an input, i.e ., put the corresponding output dr iv er in a hi-impedance mode . clear ing a trisa bit (=0) will mak e the corresponding por t a pin an output, i.e ., put the contents of the output latch on the selected pin. reading the por t a register reads the status of the pins whereas wr iting to it will wr ite to the por t latch. all wr ite oper ations are read-modify-wr ite oper ations . theref ore a wr ite to a por t implies that the por t pins are read, this v alue is modi ed, and then wr itten to the por t data latch. pin ra4 is m ultiple x ed with the timer0 module cloc k input to become the ra4/t0cki pin. the ra4/t0cki pin is a schmitt t r igger input and an open dr ain output. all other ra por t pins ha v e ttl input le v els and full cmos output dr iv ers . other por t a pins are m ultiple x ed with analog inputs and analog v ref input. the oper ation of each pin is selected b y clear ing/setting the control bits in the adcon1 register (a/d control register1). the trisa register controls the direction of the ra pins , e v en when the y are being used as analog inputs . the user m ust ensure the bits in the trisa register are maintained set when using them as analog inputs . example 3-1: initi alizing por t a bcf status, rp0 ; clrf porta ; initialize porta by ; clearing output ; data latches bsf status, rp0 ; select bank 1 movlw 0xcf ; value used to ; initialize data ; direction movwf trisa ; set ra<3:0> as inputs ; ra<5:4> as outputs ; trisa<7:6> are always ; read as '0'. figure 3-1: bloc k dia gram of ra3:ra0 and ra5 pins figure 3-2: bloc k dia gram of ra4/ t0cki pin note: on a p o w er-on reset, these pins are con- gured as analog inputs and read as '0'. data b us q d q ck q d q ck q d en p n wr p o r t wr tris data latch tris latch rd tris rd por t v ss v dd i/o pin (1) note 1: i/o pins ha v e protection diodes to v dd and v ss . analog input mode ttl input b uff er t o a/d con v er ter data b us wr por t wr tris rd por t data latch tris latch rd tris schmitt t r igger input b uff er n v ss i/o pin (1) tmr0 cloc k input note 1: i/o pin has protection diodes to v ss only . q d q ck q d q ck en q d en
pic16c72 series ds39016a -page 20 preliminary ? 1998 microchip technology inc. t able 3-1 por t a functions t able 3-2 summar y of register s associated with por t a name bit# buff er function ra0/an0 bit0 ttl input/output or analog input ra1/an1 bit1 ttl input/output or analog input ra2/an2 bit2 ttl input/output or analog input ra3/an3/ v ref bit3 ttl input/output or analog input or v ref ra4/t0cki bit4 st input/output or e xter nal cloc k input f or timer0 output is open dr ain type ra5/ ss /an4 bit5 ttl input/output or sla v e select input f or synchronous ser ial por t or analog input legend: ttl = ttl input, st = schmitt t r igger input ad dress name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 v alue on: por, bor v alue on all other resets 05h por t a ra5 ra4 ra3 ra2 ra1 ra0 --0x 0000 --0u 0000 85h trisa por t a data direction register --11 1111 --11 1111 9fh adcon1 pcfg2 pcfg1 pcfg0 ---- -000 ---- -000 legend: x = unkno wn, u = unchanged, - = unimplemented locations read as '0'. shaded cells are not used b y por t a.
pic16c72 series ? 1998 microchip technology inc. preliminary ds39016a -page 21 3.2 por tb and the trisb register por tb is an 8-bit wide bi-directional por t. the corre- sponding data direction register is trisb . setting a trisb bit (=1) will mak e the corresponding por tb pin an input, i.e ., put the corresponding output dr iv er in a hi-impedance mode . clear ing a trisb bit (=0) will mak e the corresponding por tb pin an output, i.e ., put the contents of the output latch on the selected pin. example 3-1: initia lizing por tb bcf status, rp0 ; clrf portb ; initialize portb by ; clearing output ; data latches bsf status, rp0 ; select bank 1 movlw 0xcf ; value used to ; initialize data ; direction movwf trisb ; set rb<3:0> as inputs ; rb<5:4> as outputs ; rb<7:6> as inputs each of the por tb pins has a w eak inter nal pull-up . a single control bit can tur n on all the pull-ups . this is per- f or med b y clear ing bit rbpu (option<7>). the w eak pull-up is automatically tur ned off when the por t pin is con gured as an output. the pull-ups are disab led on a p o w er-on reset. figure 3-3: bloc k dia gram of rb3:rb0 pins f our of por tb s pins , rb7:rb4, ha v e an interr upt on change f eature . only pins con gured as inputs can cause this interr upt to occur (i.e . an y rb7:rb4 pin con- gured as an output is e xcluded from the interr upt on change compar ison). the input pins (of rb7:rb4) are compared with the old v alue latched on the last read of por tb . the ?ismatch outputs of rb7:rb4 are or?d together to gener ate the rb p or t change inter- r upt with ag bit rbif (intcon<0>). this interr upt can w ak e the de vice from sleep . the user , in the interr upt ser vice routine , can clear the inter- r upt in the f ollo wing manner : a) an y read or wr ite of por tb . this will end the mismatch condition. b) clear ag bit rbif . a mismatch condition will contin ue to set ag bit rbif . reading por tb will end the mismatch condition, and allo w ag bit rbif to be cleared. the interr upt on change f eature is recommended f or w ak e-up on k e y depression oper ation and oper ations where por tb is only used f or the interr upt on change f eature . p olling of por tb is not recommended while using the interr upt on change f eature . figure 3-4: bloc k dia gram of rb7:rb4 pins data latch rbpu (2) p v dd q d ck q d ck q d en data b us wr p or t wr tris rd tris rd p or t w eak pull-up rd p or t rb0/int i/o pin (1) ttl input buff er note 1: i/o pins ha v e diode protection to v dd and v ss . 2: t o enab le w eak pull-ups , set the appropr iate tris bit(s) and clear the rbpu bit (o ption<7>). schmitt t r igger buff er tris latch data latch f rom other rbpu (2) p v dd i/o q d ck q d ck q d en q d en data b us wr p or t wr tris set rbif tris latch rd tris rd p or t rb 7 : rb 4 p ins w eak pull-up rd p or t latch ttl input buff er pin (1) note 1: i/o pins ha v e diode protection to v dd and v ss . st buff er rb7:rb6 in ser ial prog r amming mode q3 q1 2: t o enab le w eak pull-ups , set the appropr iate tris bit(s) and clear the rbpu bit (o ption<7>).
pic16c72 series ds39016a -page 22 preliminary ? 1998 microchip technology inc. t able 3-3 por tb functions t able 3-4 summar y of register s associated with por tb name bit# buff er function rb0/int bit0 ttl/st (1) input/output pin or e xter nal interr upt input. inter nal softw are prog r ammab le w eak pull-up . rb1 bit1 ttl input/output pin. inter nal softw are prog r ammab le w eak pull-up . rb2 bit2 ttl input/output pin. inter nal softw are prog r ammab le w eak pull-up . rb3 bit3 ttl input/output pin. inter nal softw are prog r ammab le w eak pull-up . rb4 bit4 ttl input/output pin (with interr upt on change). inter nal softw are prog r ammab le w eak pull-up . rb5 bit5 ttl input/output pin (with interr upt on change). inter nal softw are prog r ammab le w eak pull-up . rb6 bit6 ttl/st (2) input/output pin (with interr upt on change). inter nal softw are prog r ammab le w eak pull-up . ser ial prog r amming cloc k. rb7 bit7 ttl/st (2) input/output pin (with interr upt on change). inter nal softw are prog r ammab le w eak pull-up . ser ial prog r amming data. legend: ttl = ttl input, st = schmitt t r igger input note 1: this b uff er is a schmitt t r igger input when con gured as the e xter nal interr upt. 2: this b uff er is a schmitt t r igger input when used in ser ial prog r amming mode . ad dress name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 v alue on: por, bor v alue on all other resets 06h, 106h por tb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx xxxx uuuu uuuu 86h, 186h trisb por tb data direction register 1111 1111 1111 1111 81h, 181h option rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 legend: x = unkno wn, u = unchanged. shaded cells are not used b y por tb .
pic16c72 series ? 1998 microchip technology inc. preliminary ds39016a -page 23 3.3 por tc and the trisc register por tc is an 8-bit wide bi-directional por t. the corre- sponding data direction register is trisc . setting a trisc bit (=1) will mak e the corresponding por tc pin an input, i.e ., put the corresponding output dr iv er in a hi-impedance mode . clear ing a trisc bit (=0) will mak e the corresponding por tc pin an output, i.e ., put the contents of the output latch on the selected pin. por tc is m ultiple x ed with se v er al per ipher al functions ( t ab le 3-5 ). por tc pins ha v e schmitt t r igger input b uff ers . when enab ling per ipher al functions , care should be tak en in de ning tris bits f or each por tc pin. some per ipher als o v err ide the tris bit to mak e a pin an out- put, while other per ipher als o v err ide the tris bit to mak e a pin an input. since the tris bit o v err ide is in eff ect while the per ipher al is enab led, read-modify- wr ite instr uctions ( bsf, bcf, xorwf ) with trisc as destination should be a v oided. the user should ref er to the corresponding per ipher al section f or the correct tris bit settings . example 3-1: initia lizing por tc bcf status, rp0 ; select bank 0 clrf portc ; initialize portc by ; clearing output ; data latches bsf status, rp0 ; select bank 1 movlw 0xcf ; value used to ; initialize data ; direction movwf trisc ; set rc<3:0> as inputs ; rc<5:4> as outputs ; rc<7:6> as inputs figure 3-5: por tc bloc k dia gram (p eripheral output override) por t/ peripheral select (2) data b us wr por t wr tris rd data latch tris latch rd tris schmitt t r igger q d q ck q d en p er ipher al data out 0 1 q d q ck p n v dd v ss por t p er ipher al oe (3) p er ipher al input i/o pin (1) note 1: i/o pins ha v e diode protection to v dd and v ss . 2: p or t/p er ipher al select signal selects betw een por t data and per ipher al output. 3: p er ipher al oe (output enab le) is only activ ated if per ipher al select is activ e .
pic16c72 series ds39016a -page 24 preliminary ? 1998 microchip technology inc. t able 3-5 por tc functions t able 3-6 summar y of register s associated with por tc name bit# buff er t ype function rc0/t1oso/t1cki bit0 st input/output por t pin or timer1 oscillator output/timer1 cloc k input rc1/t1osi bit1 st input/output por t pin or timer1 oscillator input rc2/ccp1 bit2 st input/output por t pin or capture1 input/compare1 output/pwm1 output rc3/sck/scl bit3 st rc3 can also be the synchronous ser ial cloc k f or both spi and i 2 c modes . rc4/sdi/sd a bit4 st rc4 can also be the spi data in (spi mode) or data i/o (i 2 c mode). rc5/sdo bit5 st input/output por t pin or synchronous ser ial p or t data output rc6 bit6 st input/output por t pin rc7 bit7 st input/output por t pin legend: st = schmitt t r igger input ad dress name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 v alue on: por, bor v alue on all other resets 07h por tc rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 xxxx xxxx uuuu uuuu 87h trisc por tc data direction register 1111 1111 1111 1111 legend: x = unkno wn, u = unchanged.
pic16c72 series ? 1998 microchip technology inc. preliminary ds39016a -page 25 4.0 timer0 module the timer0 module timer/counter has the f ollo wing f ea- tures: 8-bit timer/counter readab le and wr itab le inter nal or e xter nal cloc k select edge select f or e xter nal cloc k 8-bit softw are prog r ammab le prescaler interr upt on o v er o w from ffh to 00h figure 4-1 is a simpli ed b loc k diag r am of the timer0 module . additional inf or mation on timer modules is a v ailab le in the picmicro mid-range mcu ref erence man ual, ds33023. 4.1 t imer0 operation timer0 can oper ate as a t imer or as a c ounter . timer mode is selected b y clear ing bit t0cs (option_reg<5>). in timer mode , the timer0 mod- ule will increment e v er y instr uction cycle (without pres- caler). if the tmr0 register is wr itten, the increment is inhibited f or the f ollo wing tw o instr uction cycles . the user can w or k around this b y wr iting an adjusted v alue to the tmr0 register . counter mode is selected b y setting bit t0cs (option_reg<5>). in counter mode , timer0 will increment either on e v er y r ising or f alling edge of pin ra4/t0cki. the incrementing edge is deter mined b y the timer0 source edge select bit t0se (option_reg<4>). clear ing bit t0se selects the r is- ing edge . restr ictions on the e xter nal cloc k input are discussed in belo w . when an e xter nal cloc k input is used f or timer0, it m ust meet cer tain requirements . the requirements ensure the e xter nal cloc k can be synchroniz ed with the inter nal phase cloc k (t osc ). also , there is a dela y in the actual incrementing of timer0 after synchronization. additional inf or mation on e xter nal cloc k requirements is a v ailab le in the picmicro mid-range mcu ref er- ence man ual , ds33023. 4.2 pre scaler an 8-bit counter is a v ailab le as a prescaler f or the timer0 module , or as a postscaler f or the w atchdog timer , respectiv ely ( figure 4-2 ). f or simplicity , this counter is being ref erred to as ?rescaler throughout this data sheet. note that there is only one prescaler a v ailab le which is m utually e xclusiv ely shared betw een the timer0 module and the w atchdog timer . thus , a prescaler assignment f or the timer0 module means that there is no prescaler f or the w atchdog timer , and vice-v ersa. the prescaler is not readab le or wr itab le . the psa and ps2:ps0 bits (option_reg<3:0>) deter mine the prescaler assignment and prescale r atio . clear ing bit psa will assign the prescaler to the timer0 module . when the prescaler is assigned to the timer0 module , prescale v alues of 1:2, 1:4, ..., 1:256 are selectab le . setting bit psa will assign the prescaler to the w atch- dog timer (wdt). when the prescaler is assigned to the wdt , prescale v alues of 1:1, 1:2, ..., 1:128 are selectab le . when assigned to the timer0 module , all instr uctions wr iting to the tmr0 register (e .g. clrf 1, movwf 1, bsf 1,x ....etc.) will clear the prescaler . when assigned to wdt , a clrwdt instr uction will clear the prescaler along with the wdt . figure 4-1: timer0 blo c k dia gram note: wr iting to tmr0 when the prescaler is assigned to timer0 will clear the prescaler count, b ut will not change the prescaler assignment. note 1: t0cs , t0se, psa, ps2:ps0 (option_reg<5:0>). 2: the prescaler is shared with w atchdog timer (ref er to figure 4-2 f or detailed b loc k diag r am). ra4/t0cki t0se 0 1 1 0 pin t0cs f osc /4 prog r ammab le prescaler sync with inter nal cloc ks tmr0 psout (2 cycle dela y) psout data b us 8 psa ps2, ps1, ps0 set interr upt ag bit t0if on o v er o w 3
pic16c72 series ds39016a -page 26 preliminary ? 1998 microchip technology inc. 4.2.1 switching pre scaler assignment the prescaler assignment is fully under softw are con- trol, i.e ., it can be changed ?n the y dur ing prog r am e x ecution. 4.3 timer0 in terrupt the tmr0 interr upt is gener ated when the tmr0 reg- ister o v er o ws from ffh to 00h. this o v er o w sets bit t0if (intcon<2>). the interr upt can be mask ed b y clear ing bit t0ie (intcon<5>). bit t0if m ust be cleared in softw are b y the timer0 module interr upt ser- vice routine bef ore re-enab ling this interr upt. the tmr0 interr upt cannot a w ak en the processor from sleep since the timer is shut off dur ing sleep . figure 4-2: bloc k dia gra m of the timer0/wdt prescaler t able 4-1 register s associated with timer0 note: t o a v oid an unintended de vice reset , a speci c instr uction sequence (sho wn in the picmicro mid-range mcu ref erence man ual , ds3023) m ust be e x ecuted when changing the prescaler assignment from timer0 to the wdt . this sequence m ust be f ollo w ed e v en if the wdt is disab led. ad dress name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 v alue on: por, bor v alue on all other resets 01h,101h tmr0 timer0 module s register xxxx xxxx uuuu uuuu 0bh,8bh, 10bh,18bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 81h,181h option_ r eg rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 85h trisa por t a data direction register --11 1111 --11 1111 legend: x = unkno wn, u = unchanged, - = unimplemented locations read as '0'. shaded cells are not used b y timer0. ra4/t0cki t0se pin m u x clk out (=f osc/4) sync 2 cycles tmr0 reg 8-bit prescaler 8 - to - 1mux m u x m u x w atchdog timer psa 0 1 0 1 wdt time-out ps2:ps0 8 note: t0cs , t0se, psa, ps2:ps0 are (option_reg<5:0>). psa wdt enab le bit m u x 0 1 0 1 data bus set ag bit t0if on ov er o w 8 psa t0cs
pic16c72 series ? 1998 microchip technology inc. preliminary ds39016a -page 27 5.0 timer1 module the timer1 module timer/counter has the f ollo wing f ea- tures: 16-bit timer/counter (t w o 8-bit registers; tmr1h and tmr1l) readab le and wr itab le (both registers) inter nal or e xter nal cloc k select interr upt on o v er o w from ffffh to 0000h reset from ccp module tr igger timer1 has a control register , sho wn in figure 5-1 . timer1 can be enab led/disab led b y setting/clear ing control bit tmr1on (t1con<0>). figure 5-2 is a simpli ed b loc k diag r am of the timer1 module . additional inf or mation on timer modules is a v ailab le in the picmicro mid-range mcu ref erence man ual, ds33023. 5.1 t imer1 operation timer1 can oper ate in one of these modes: as a timer as a synchronous counter as an asynchronous counter the oper ating mode is deter mined b y the cloc k select bit, tmr1cs (t1con<1>). in timer mode , timer1 increments e v er y instr uction cycle . in counter mode , it increments on e v er y r ising edge of the e xter nal cloc k input. when the timer1 oscillator is enab led (t1oscen is set), the rc1/t1osi and rc0/t1oso/t1cki pins become inputs . that is , the trisc<1:0> v alue is ignored. timer1 also has an inter nal ?eset input? this reset can be gener ated b y the ccp module ( section 7.0 ). figure 5-1: t1con: timer1 c ontr ol register (ad dress 10 h) u-0 u-0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 t1ck ps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on r = readab le bit w = wr itab le bit u = unimplemented bit, read as ? - n = v alue at por reset bit7 bit0 bit 7-6: unimplemented: read as '0' bit 5-4: t1ckps1:t1ckps0 : timer1 input cloc k prescale select bits 11 = 1:8 prescale v alue 10 = 1:4 prescale v alue 01 = 1:2 prescale v alue 00 = 1:1 prescale v alue bit 3: t1oscen : timer1 oscillator enab le control bit 1 = oscillator is enab led 0 = oscillator is shut off note: the oscillator in v er ter and f eedbac k resistor are tur ned off to eliminate po w er dr ain bit 2: t1sync : timer1 exter nal cloc k input synchronization control bit tmr1cs = 1 1 = do not synchroniz e e xter nal cloc k input 0 = synchroniz e e xter nal cloc k input tmr1cs = 0 this bit is ignored. timer1 uses the inter nal cloc k when tmr1cs = 0. bit 1: tmr1cs : timer1 cloc k source select bit 1 = exter nal cloc k from pin rc0/t1oso/t1cki (on the r ising edge) 0 = inter nal cloc k (f osc /4) bit 0: tmr1on : timer1 on bit 1 = enab les timer1 0 = stops timer1
pic16c72 series ds39016a -page 28 preliminary ? 1998 microchip technology inc. figure 5-2: timer1 bloc k dia gram tmr1h tmr1l t1osc t1sync tmr1cs t1ckps1:t1ckps0 sleep input t1oscen enab le oscillator (1) f osc /4 inter nal cloc k tmr1 on on/off prescaler 1, 2, 4, 8 synchroniz e det 1 0 0 1 synchroniz ed cloc k input 2 rc0/t1oso/t1cki rc1/t1osi note 1: when the t1oscen bit is cleared, the in v er ter and f eedbac k resistor are tur ned off . this eliminates po w er dr ain. set ag bit tmr1if on ov er o w tmr1
pic16c72 series ? 1998 microchip technology inc. preliminary ds39016a -page 29 5.2 timer1 oscillator a cr ystal oscillator circuit is b uilt in betw een pins t1osi (input) and t1oso (ampli er output). it is enab led b y setting control bit t1oscen (t1con<3>). the oscilla- tor is a lo w po w er oscillator r ated up to 200 khz. it will contin ue to r un dur ing sleep . it is pr imar ily intended f or a 32 khz cr ystal. t ab le 5-1 sho ws the capacitor selection f or the timer1 oscillator . the timer1 oscillator is identical to the lp oscillator . the user m ust pro vide a softw are time dela y to ensure proper oscillator star t-up . t able 5-1 capacitor selection f or the timer1 oscillator 5.3 timer1 interrupt the tmr1 register pair (tmr1h:tmr1l) increments from 0000h to ffffh and rolls o v er to 0000h. the tmr1 interr upt, if enab led, is gener ated on o v er o w which is latched in interr upt ag bit tmr1if (pir1<0>). this interr upt can be enab led/disab led b y setting/clear- ing tmr1 interr upt enab le bit tmr1ie (pie1<0>). 5.4 resetting timer1 using a ccp t rig g er output if the ccp module is con gured in compare mode to gener ate a ?pecial e v ent tr igger" (ccp1m3:ccp1m0 = 1011 ), this signal will reset timer1 and star t an a/d con v ersion (if the a/d module is enab led). timer1 m ust be con gured f or either timer or synchro- niz ed counter mode to tak e adv antage of this f eature . if timer1 is r unning in asynchronous counter mode , this reset oper ation ma y not w or k. in the e v ent that a wr ite to timer1 coincides with a spe- cial e v ent tr igger from ccp1, the wr ite will tak e prece- dence . in this mode of oper ation, the ccpr1h:ccpr1l regis- ters pair eff ectiv ely becomes the per iod register f or timer1. t able 5-2 register s associated with timer1 as a timer/counter osc t ype freq c1 c2 lp 32 khz 33 pf 33 pf 100 khz 15 pf 15 pf 200 khz 15 pf 15 pf these v alues are f or design guidance onl y . cr ystals t ested: 32.768 khz epson c-001r32.768k-a 20 ppm 100 khz epson c-2 100.00 kc-p 20 ppm 200 khz std xtl 200.000 khz 20 ppm note 1: higher capacitance increases the stability of oscillator b ut also increases the star t-up time . 2: since each resonator/cr ystal has its o wn char acter istics , the user should consult the resonator/cr ystal man uf acturer f or appropr i- ate v alues of e xter nal components . note: the special e v ent tr iggers from the ccp1 module will not set interr upt ag bit tmr1if (pir1<0>). ad dress name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 v alue on: por, bor v alue on all other resets 0bh,8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 (1) adif (1) (1) sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 (1) adie (1) (1) sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 0eh tmr1l holding register f or the least signi cant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 0fh tmr1h holding register f or the most signi cant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 10h t1con t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on --00 0000 --uu uuuu legend: x = unkno wn, u = unchanged, - = unimplemented read as '0'. shaded cells are not used b y the timer1 module . note 1: these bits are unimplemented, read as '0'.
pic16c72 series ds39016a -page 30 preliminary ? 1998 microchip technology inc. notes:
pic16c72 series ? 1998 microchip technology inc. preliminary ds39016a -page 31 6.0 timer2 module the timer2 module timer has the f ollo wing f eatures: 8-bit timer (tmr2 register) 8-bit per iod register (pr2) readab le and wr itab le (both registers) softw are prog r ammab le prescaler (1:1, 1:4, 1:16) softw are prog r ammab le postscaler (1:1 to 1:16) interr upt on tmr2 match of pr2 ssp module optional use of tmr2 output to gen- er ate cloc k shift timer2 has a control register , sho wn in figure 6-2 . timer2 can be shut off b y clear ing control bit tmr2on (t2con<2>) to minimiz e po w er consumption. figure 6-1 is a simpli ed b loc k diag r am of the timer2 module . additional inf or mation on timer modules is a v ailab le in the picmicro mid-range mcu ref erence man ual, ds33023. 6.1 t imer2 operation timer2 can be used as the pwm time-base f or pwm mode of the ccp module . the tmr2 register is readab le and wr itab le , and is cleared on an y de vice reset. the input cloc k (f osc /4) has a prescale option of 1:1, 1:4 or 1:16, selected b y control bits t2ckps1:t2ckps0 (t2con<1:0>). the match output of tmr2 goes through a 4-bit postscaler (which giv es a 1:1 to 1:16 scaling inclusiv e) to gener ate a tmr2 interr upt (latched in ag bit tmr2if , (pir1<1>)). the prescaler and postscaler counters are cleared when an y of the f ollo wing occurs: a wr ite to the tmr2 register a wr ite to the t2con register an y de vice reset (p o w er-on reset, mclr reset, w atchdog timer reset, or bro wn-out reset) tmr2 is not cleared when t2con is wr itten. 6.2 timer2 interrupt the timer2 module h as an 8-bit per iod register pr2. timer2 increments from 00h until it matches pr2 and then resets to 00h on the ne xt increment cycle . pr2 is a readab le and wr itab le register . the pr2 register is ini- tializ ed to ffh upon reset. 6.3 output of tmr2 the output of tmr2 (bef ore the postscaler) is f ed to the synchronous ser ial p or t module which optionally uses it to gener ate shift cloc k. figure 6-1: timer2 bloc k dia gram compar ator tmr2 sets ag tmr2 reg output (1) reset p ostscaler prescaler pr2 reg 2 f osc /4 1:1 1:16 1: 1, 1: 4, 1: 16 eq 4 bit tmr2if note 1: tmr2 register output can be softw are selected b y the ssp module as a baud cloc k. to
pic16c72 series ds39016a -page 32 preliminary ? 1998 microchip technology inc. figure 6-2: t2con: timer2 contr ol register (ad dress 12 h ) t able 6-1 register s associated with timer2 as a timer/counter u-0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 t out ps3 t outps2 t outps1 t outps0 tmr2on t2ckps1 t2ckps0 r = readab le bit w = wr itab le bit u = unimplemented bit, read as ? - n = v alue at por reset bit7 bit0 bit 7: unimplemented: read as '0' bit 6-3: t outps3:t outps0 : timer2 output p ostscale select bits 0000 = 1:1 p ostscale 0001 = 1:2 p ostscale 1111 = 1:16 p ostscale bit 2: tmr2on : timer2 on bit 1 = timer2 is on 0 = timer2 is off bit 1-0: t2ckps1:t2ckps0 : timer2 cloc k prescale select bits 00 = prescaler is 1 01 = prescaler is 4 1x = prescaler is 16 ad dress name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 v alue on: por, bor v alue on all other resets 0bh,8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 (1) adif (1) (1) sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 (1) adie (1) (1) sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 11h tmr2 timer2 module s register 0000 0000 0000 0000 12h t2con t outps3 t outps2 t outps1 t outps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 92h pr2 timer2 p er iod register 1111 1111 1111 1111 legend: x = unkno wn, u = unchanged, - = unimplemented read as '0'. shaded cells are not used b y the timer2 module . 2: these bits are unimplemented, read as '0'.
pic16c72 series ? 1998 microchip technology inc. preliminary ds39016a -page 33 7.0 capture/compare/pwm (ccp) module the ccp (capture/compare/pwm) module contains a 16-bit register which can oper ate as a 16-bit capture register , as a 16-bit compare register or as a pwm master/sla v e duty cycle register . t ab le 7-1 sho ws the timer resources of the ccp module modes . capture/com pare/pwm register1 (ccpr1) is com- pr ised of tw o 8-bit registers: ccpr1l (lo w b yte) and ccpr1h (high b yte). the ccp1con register controls the oper ation of ccp1. all are readab le and wr itab le . additional inf or mation on the ccp module is a v ailab le in the picmicro mid-range mcu ref erence man ual, ds33023. t able 7-1 ccp mode - timer r esour ce figure 7-1: ccp1con register (ad dress 17 h ) ccp mode timer resour ce capture compare pwm timer1 timer1 timer2 u-0 u-0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 ccp1x ccp1y ccp1m3 ccp1m2 ccp1m1 ccp1m0 r = readab le bit w = wr itab le bit u = unimplemented bit, read as ? - n = v alue at por reset bit7 bit0 bit 7-6: unimplemented : read as '0' bit 5-4: ccp1x:ccp1y : pwm least signi cant bits capture mode: un used compare mode: un used pwm mode: these bits are the tw o lsbs of the pwm duty cycle . the eight msbs are f ound in ccpr1l. bit 3-0: ccp1m3:ccp1m0 : ccp1 mode select bits 0000 = capture/compare/pwm off (resets ccp1 module) 0100 = capture mode , e v er y f alling edge 0101 = capture mode , e v er y r ising edge 0110 = capture mode , e v er y 4th r ising edge 0111 = capture mode , e v er y 16th r ising edge 1000 = compare mode , set output on match (ccp1if bit is set) 1001 = compare mode , clear output on match (ccp1if bit is set) 1010 = compare mode , gener ate softw are interr upt on match (ccp1if bit is set, ccp1 pin is unaff ected) 1011 = compare mode , tr igger special e v ent (ccp1if bit is set; ccp1 resets tmr1 and star ts an a/d con v ersion (if a/d module is enab led)) 11xx = pwm mode
pic16c72 series ds39016a -page 34 preliminary ? 1998 microchip technology inc. 7.1 capture mode in capture mode , ccpr1h:ccpr1l captures the 16-bit v alue of the tmr1 register when an e v ent occurs on pin rc2/ccp1. an e v ent is de ned as: e v er y f alling edge e v er y r ising edge e v er y 4th r ising edge e v er y 16th r ising edge an e v ent is selected b y control bits ccp1m3:ccp1m0 (ccp1con<3:0>). when a capture is made , the inter- r upt request ag bit ccp1if (pir1<2>) is set. it m ust be cleared in softw are . if another capture occurs bef ore the v alue in register ccpr1 is read, the old captured v alue will be lost. 7.1.1 ccp pin configur ation in capture mode , the rc2/ccp1 pin should be con g- ured as an input b y setting the trisc<2> bit. figure 7-2: capture mode operation bloc k dia gram 7.1.2 timer1 mode selection timer1 m ust be r unning in timer mode or synchroniz ed counter mode f or the ccp module to use the capture f eature . in asynchronous counter mode , the capture oper ation ma y not w or k. 7.1.3 softw are interr upt when the capture mode is changed, a f alse capture interr upt ma y be gener ated. the user should k eep bit ccp1ie (pie1<2>) clear to a v oid f alse interr upts and should clear the ag bit ccp1if f ollo wing an y such change in oper ating mode . 7.1.4 ccp prescaler there are f our prescaler settings , speci ed b y bits ccp1m3:ccp1m0. whene v er the ccp module is tur ned off , or the ccp module is not in capture mode , the prescaler counter is cleared. this means that an y reset will clear the prescaler counter . switching from one capture prescaler to another ma y gener ate an interr upt. also , the prescaler counter will not be cleared, theref ore the rst capture ma y be from a non-z ero prescaler . example 7-1 sho ws the recom- mended method f or s witching betw een capture pres- calers . this e xample also clears the prescaler counter and will not gener ate the ? alse interr upt. example 7-1: changing b etween capture prescaler s clrf ccp1con ;turn ccp module off movlw new_capt_ps ;load the w reg with ; the new prescaler ; mode value and ccp on movwf ccp1con ;load ccp1con with this ; value note: if the rc2/ccp1 is con gured as an out- put, a wr ite to the por t can cause a capture condition. ccpr1h ccpr1l tmr1h tmr1l set ag bit ccp1if (pir1<2>) capture enab le q s ccp1con<3:0> rc2/ccp1 prescaler ? 1, 4, 16 and edge detect pin
pic16c72 series ? 1998 microchip technology inc. preliminary ds39016a -page 35 7.2 compare mode in compare mode , the 16-bit ccpr1 register v alue is constantly compared against the tmr1 register pair v alue . when a match occurs , the rc2/ccp1 pin is: dr iv en high dr iv en lo w re mains unchanged the action on the pin is based on the v alue of control bits ccp1m3:ccp1m0 (ccp1con<3:0>). at the same time , interr upt ag bit ccp1if is set. figure 7-3: compare mode operation bloc k dia gram 7.2.1 ccp pin configur ation the user m ust con gure the rc2/ccp1 pin as an out- put b y clear ing the trisc<2> bit. 7.2.2 timer1 mode selection timer1 m ust be r unning in timer mode or synchro- niz ed counter mode if the ccp module is using the compare f eature . in asynchronous counter mode , the compare oper ation ma y not w or k. 7.2.3 softw are interr upt mode when gener ate softw are interr upt is chosen the ccp1 pin is not aff ected. only a ccp interr upt is gener ated (if enab led). 7.2.4 special ev ent t r igger in this mode , an inter nal hardw are tr igger is gener ated which ma y be used to initiate an action. the special e v ent tr igger output of ccp1 resets the tmr1 register pair . this allo ws the ccpr1 register to eff ectiv ely be a 16-bit prog r ammab le per iod register f or timer1. the special tr igger output of ccp1 resets the tmr1 register pair , and star ts an a/d con v ersion (if the a/d module is enab led). t able 7-2 register s associated with capture , compare , and timer1 ccpr1h ccpr1l tmr1h tmr1l compar ator q s r output logic special ev ent t r igger set ag bit ccp1if (pir1<2>) match rc2/ccp1 trisc<2> ccp1con<3:0> mode select output enab le pin special e v ent tr igger will: reset timer1, b ut not set interr upt ag bit tmr1if (pir1<0>), and set bit go/ done (adcon0<2>) which star ts an a/d con v ersion note: clear ing the ccp1con register will f orce the rc2/ccp1 compare output latch to the def ault lo w le v el. this is not the data latch. note: the special e v ent tr igger from the ccp1 module will not set interr upt ag bit tmr1if (pir1<0>). ad dress name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 v alue on: por, bor v alue on all other resets 0bh,8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 (1) adif (1) (1) sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 (1) adie (1) (1) sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 87h trisc por tc data direction register 1111 1111 1111 1111 0eh tmr1l holding register f or the least signi cant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 0fh tmr1h holding register f or the most signi cant byte of the 16-bit tmr1register xxxx xxxx uuuu uuuu 10h t1con t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on --00 0000 --uu uuuu 15h ccpr1l capture/compare/pwm register1 (lsb) xxxx xxxx uuuu uuuu 16h ccpr1h capture/compare/pwm register1 (msb) xxxx xxxx uuuu uuuu 17h ccp1con ccp1x ccp1y ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 legend: x = unkno wn, u = unchanged, - = unimplemented read as '0'. shaded cells are not used b y capture and timer1. note 1: these bits/registers are unimplemented, read as '0'.
pic16c72 series ds39016a -page 36 preliminary ? 1998 microchip technology inc. 7.3 pwm m ode in pulse width modulation (pwm) mode , the ccp1 pin produces up to a 10-bit resolution pwm output. since the ccp1 pin is m ultiple x ed with the por tc data latch, the trisc<2> bit m ust be cleared to mak e the ccp1 pin an output. figure 7-4 sho ws a simpli ed b loc k diag r am of the ccp module in pwm mode . f or a step b y step procedure on ho w to set up the ccp module f or pwm oper ation, see section 7.3.3 . figure 7-4: simp lified pwm bloc k dia gram a pwm output ( figure 7-5 ) has a time base (per iod) and a time that the output sta ys high (duty cycle). the frequency of the pwm is the in v erse of the per iod (1/per iod). figure 7-5: pwm output 7.3.1 pwm per iod the pwm per iod is speci ed b y wr iting to the pr2 reg- ister . the pwm per iod can be calculated using the f ol- lo wing f or m ula: pwm period = [(pr2) + 1] 4 t osc (tmr2 pr escale value) pwm frequency is de ned as 1 / [pwm per iod]. when tmr2 is equal to pr2, the f ollo wing three e v ents occur on the ne xt increment cycle: tmr2 is cleared the ccp1 pin is set (e xception: if pwm duty cycle = 0%, the ccp1 pin will not be set) the pwm duty cycle is latched from ccpr1l into ccpr1h 7.3.2 pwm duty cycle the pwm duty cycle is speci ed b y wr iting to the ccpr1l register and to the ccp1con<5:4> bits . up to 10-bit resolution is a v ailab le: the ccpr1l contains the eight msbs and the ccp1con<5:4> contains the tw o lsbs . this 10-bit v alue is represented b y ccpr1l:ccp1con<5:4>. the f ollo wing equation is used to calculate the pwm duty cycle in time: pwm duty cycle = (ccpr1l:ccp1con<5:4>) t osc (tmr2 pr escale value) ccpr1l and ccp1con<5:4> can be wr itten to at an y time , b ut the duty cycle v alue is not latched into ccpr1h until after a match betw een pr2 and tmr2 occurs (i.e ., the per iod is complete). in pwm mode , ccpr1h is a read-only register . the ccpr1h register and a 2-bit inter nal latch are used to doub le b uff er the pwm duty cycle . this doub le b uff er ing is essential f or glitchless pwm oper ation. when the ccpr1h and 2-bit latch match tmr2 con- catenated with an inter nal 2-bit q cloc k or 2 bits of the tmr2 prescaler , the ccp1 pin is cleared. maxim um pwm resolution (bits) f or a giv en pwm frequency: note: clear ing the ccp1con register will f orce the ccp1 pwm output latch to the def ault lo w le v el. this is not the por tc i/o data latch. ccpr1l ccpr1h (sla v e) compar ator tmr2 compar ator pr2 (note 1) r q s duty cycle registers ccp1con<5:4> clear timer , ccp1 pin and latch d .c . trisc< 2> rc 2/ ccp1 note 1 : 8-bit timer is concatenated with 2-bit inter nal q cloc k or 2 bits of the prescaler to create 10-bit time -b ase . p er iod duty cycle tmr2 = pr2 tmr2 = duty cycle tmr2 = pr2 note: the timer2 postscaler (see section 6.0 ) is not used in the deter mination of the pwm frequency . the postscaler could be used to ha v e a ser v o update r ate at a diff erent fre- quency than the pwm output. note: if the pwm duty cycle v alue is longer than the pwm per iod the ccp1 pin will not be cleared. log ( f pwm log ( 2) f osc ) bits =
pic16c72 series ? 1998 microchip technology inc. preliminary ds39016a -page 37 f or an e xample pwm per iod and duty cycle calcula- tion, see the picmicro mid-range mcu ref erence man ual (ds33023). 7.3.3 set-up f or pwm oper ation the f ollo wing steps should be tak en when con gur ing the ccp module f or pwm oper ation: 1. set the pwm per iod b y wr iting to the pr2 regis- ter . 2. set the pwm duty cycle b y wr iting to the ccpr1l register and ccp1con<5:4> bits . 3. mak e the ccp1 pin an output b y clear ing the trisc<2> bit. 4. set the tmr2 prescale v alue and enab le timer2 b y wr iting to t2con. 5. con gure the ccp1 module f or pwm oper ation. t able 7-3 example pwm frequencies and resoluti ons at 20 mh z t able 7-4 register s associated with pwm and timer2 pwm frequenc y 1.22 khz 4.88 khz 19.53 khz 78.12 khz 156.3 khz 208.3 khz timer prescaler (1, 4, 16) 16 4 1 1 1 1 pr2 v alue 0xff 0xff 0xff 0x3f 0x1f 0x17 maxim um resolution (bits) 10 10 10 8 7 5.5 ad dress name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 v alue on: por, bor v alue on all other resets 0bh,8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 (1) adif (1) (1) sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 (1) adie (1) (1) sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 87h trisc por tc data direction register 1111 1111 1111 1111 11h tmr2 timer2 module s register 0000 0000 0000 0000 92h pr2 timer2 module s per iod register 1111 1111 1111 1111 12h t2con t outps 3 t outps 2 t outps 1 t outps 0 tmr2o n t2ckps 1 t2ckps 0 -000 0000 -000 0000 15h ccpr1l capture/compare/pwm register1 (lsb) xxxx xxxx uuuu uuuu 16h ccpr1h capture/compare/pwm register1 (msb) xxxx xxxx uuuu uuuu 17h ccp1con ccp1x ccp1y ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 legend: x = unkno wn, u = unchanged, - = unimplemented read as '0'. shaded cells are not used b y pwm and timer2. note 1: these bits/registers are unimplemented, read as '0'.
pic16c72 series ds39016a -page 38 preliminary ? 1998 microchip technology inc. notes:
pic16c72 series ? 1998 microchip technology inc. preliminary ds39016a -page 39 8.0 sync hr onous serial p or t (ssp) module 8.1 ssp mod ule over vie w the synchronous ser ial p or t (ssp) module is a ser ial interf ace useful f or comm unicating with other per iph- er al or microcontroller de vices . these per ipher al de vices ma y be ser ial eepr oms , shift registers , dis- pla y dr iv ers , a/d con v er ters , etc. the ssp module can oper ate in one of tw o modes: ser ial p er ipher al interf ace (spi) inter-integ r ated circuit (i 2 c) the ssp module in i 2 c mode w or ks the same in all pic16c72 ser ies de vices that ha v e an ssp module . ho w e v er the ssp module in spi mode has diff erences betw een the pic16c72 and the pic16cr72 de vice . the register de nitions and oper ational descr iption of spi mode has been split into tw o sections because of the diff erences betw een the pic16c72 and the pic16cr72 de vice . the def ault reset v alues of both the spi modules is the same regardless of the de vice: 8.2 spi mode f or pic16c72 .................................. 40 8.3 spi mode f or pic16cr72 ............................... 43 8.4 ssp i 2 c oper ation .......................................... 47 f or an i 2 c ov er vie w , ref er to the picmicro mid- range mcu ref erence man ual (ds33023). also , ref er to application note an578, ? se of the ssp module in the i 2 c multi-master en vironment.
pic16c72 series ds39016a -page 40 preliminary ? 1998 microchip technology inc. 8.2 spi mode f or pic16c72 this section contains register de nitions and oper a- tional char acter istics of the spi module on the pic16c72 de vice only . additional inf or mation on spi oper ation ma y be f ound in the picmicro mid-range mcu ref erence man ual , ds33023. figure 8-1: sspst a t : sync serial p or t st atus register (ad dress 94 h ) (pic16c72) u-0 u-0 r-0 r-0 r-0 r-0 r-0 r-0 d/ a p s r/ w u a bf r = readab le bit w = wr itab le bit u = unimplemented bit, read as ? - n = v alue at por reset bit7 bit0 bit 7- 6: unimplemented : read as '0' bit 5: d / a : data/address bit (i 2 c mode only) 1 = indicates that the last b yte receiv ed or tr ansmitted w as data 0 = indicates that the last b yte receiv ed or tr ansmitted w as address bit 4: p : stop bit (i 2 c mode only . this bit is cleared when the ssp module is disab led, sspen is cleared) 1 = indicates that a stop bit has been detected last (this bit is '0' on reset) 0 = stop bit w as not detected last bit 3: s : star t bit (i 2 c mode only . this bit is cleared when the ssp module is disab led, sspen is cleared) 1 = indicates that a star t bit has been detected last (this bit is '0' on reset) 0 = star t bit w as not detected last bit 2: r / w : read/wr ite bit inf or mation (i 2 c mode only) this bit holds the r/w bit inf or mation f ollo wing the last address match. this bit is v alid from the address match to the ne xt star t bit, stop bit, or a ck bit. 1 = read 0 = wr ite bit 1: u a : update address (10-bit i 2 c mode only) 1 = indicates that the user needs to update the address in the ssp add register 0 = address does not need to be updated bit 0: b f : buff er full status bit receiv e (spi and i 2 c modes) 1 = receiv e complete , sspb uf is full 0 = receiv e not complete , sspb uf is empty t r ansmit (i 2 c mode only) 1 = t r ansmit in prog ress , sspb uf is full 0 = t r ansmit complete , sspb uf is empty
pic16c72 series ? 1998 microchip technology inc. preliminary ds39016a -page 41 figure 8-2: sspcon: sync s erial p or t contr ol register (ad dress 14 h ) (pic16c72) r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 wcol sspo v sspen ckp sspm3 sspm2 sspm1 sspm0 r = readab le bit w = wr itab le bit u = unimplemented bit, read as ? - n = v alue at por reset bit7 bit0 bit 7: wc ol : wr ite collision detect bit 1 = the sspb uf register is wr itten while it is still tr ansmitting the pre vious w ord (m ust be cleared in softw are) 0 = no collision bit 6: ssp o v : receiv e ov er o w detect bit in spi mode 1 = a ne w b yte is receiv ed while the sspb uf register is still holding the pre vious data. in case of o v er- o w , the data in sspsr register is lost. ov er o w can only occur in sla v e mode . the user m ust read the sspb uf , e v en if only tr ansmitting data, to a v oid setting o v er o w . in master o per ation, the o v er o w bit is not set since each ne w reception (and tr ansmission) is initiated b y wr iting to the sspb uf register . 0 = no o v er o w in i 2 c mode 1 = a b yte is receiv ed while the sspb uf register is still holding the pre vious b yte . sspo v is a "don? care" in tr ansmit mode . sspo v m ust be cleared in softw are in either mode . 0 = no o v er o w bit 5: ss pen : synchronous ser ial p or t enab le bit in spi mode 1 = enab les ser ial por t and con gures sck, sdo , and sdi as ser ial por t pins 0 = disab les ser ial por t and con gures these pins as i/o por t pins in i 2 c mode 1 = enab les the ser ial por t and con gures the sd a and scl pins as ser ial por t pins 0 = disab les s er ial por t and con gures these pins as i/o por t pins in both modes , when enab led, these pins m ust be proper ly con gured as input or output. bit 4: ck p : cloc k p olar ity select bit in spi mode 1 = idle state f or cloc k is a high le v el. t r ansmit happens on f alling edge , receiv e on r ising edge . 0 = idle state f or cloc k is a lo w le v el. t r ansmit happens on r ising edge , receiv e on f alling edge . in i 2 c mode sck release control 1 = enab le cloc k 0 = holds cloc k lo w (cloc k stretch) (used to ensure data setup time) bit 3-0: ssp m3:sspm0 : synchronous ser ial p or t mode select bits 0000 = spi master o per ation, cloc k = f osc/4 0001 = spi master o per ation, cloc k = f osc/16 0010 = spi master o per ation, cloc k = f osc/64 0011 = spi master o per ation, cloc k = tmr2 output/2 0100 = spi sla v e mode , cloc k = sck pin. ss pin control enab led. 0101 = spi sla v e mode , cloc k = sck pin. ss pin control disab led. ss can be used as i/o pin. 0110 = i 2 c sla v e mode , 7-bit address 0111 = i 2 c sla v e mode , 10-bit address 1011 = i 2 c f ir mw are controlled master o per ation (sla v e idle) 1110 = i 2 c sla v e mode , 7-bit address with star t and stop bit interr upts enab led 1111 = i 2 c sla v e mode , 10-bit address with star t and stop bit interr upts enab led
pic16c72 series ds39016a -page 42 preliminary ? 1998 microchip technology inc. 8.2.1 oper ation of ssp module in spi mode - pic16c72 a b loc k diag r am of the ssp module in spi mode is sho wn in figure 8-3 . the spi mode allo ws 8-bits of data to be synchro- nously tr ansmitted and receiv ed sim ultaneously . t o accomplish comm unication, typically three pins are used: s er ial d ata out (sdo) rc5/sdo ser ial data in (sdi) rc4/sdi/sd a ser ial cloc k (sck) rc3/sck/scl additionally a f our th pin ma y be used when in a sla v e mode of oper ation: sla v e select ( ss ) ra5/ ss /an4 when initializing the spi, se v er al options need to be speci ed. this is done b y prog r amming the appropr iate control bits in the sspcon register (sspcon<5:0>). these control bits allo w the f ollo wing to be speci ed: ma ster op er ation (sck is the cloc k output) sla v e mode (sck is the cloc k input) cloc k p olar ity (output/input data on the rising/ f alling edge of sck) cloc k rate (master o per ation only) sla v e select mode (sla v e mode only) t o enab le the ser ial por t, ssp enab le bit sspen (sspcon<5>) m ust be set. t o reset or recon gure spi mode , clear enab le bit sspen, re-initializ e sspcon register , and then set enab le bit sspen. this con g- ures the sdi, sdo , sck, and ss pins as ser ial por t pins . f or the pins to beha v e as the ser ial por t function, the y m ust ha v e their data direction bits (in the tris reg- ister) appropr iately prog r ammed. that is: sdi m ust ha v e trisc<4> set sdo m ust ha v e trisc<5> cleared sck (master o per ation) m ust ha v e trisc<3> cleared sck (sla v e mode) m ust ha v e trisc<3> set ss m ust ha v e trisa<5> set (if implemented) figure 8-3: ssp bloc k dia gram (spi mode) t able 8-1 register s associated with spi operation read wr ite inter nal data b us rc4/ sdi /sd a rc5/ sdo ra5 / ss /an4 rc3/ sck / sspsr reg sspb uf reg sspm3:sspm0 bit0 shift cloc k ss control enab le edge select cloc k select tmr2 output t cy prescaler 4, 16, 64 trisc<3> 2 edge select 2 4 scl ad dress name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 v alue on: por, bor v alue on all other resets 0bh,8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 (1) adif (1) (1) sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 (1) adie (1) (1) sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 87h trisc por tc data direction register 1111 1111 1111 1111 13h sspb uf synchronous ser ial p or t receiv e buff er/t r ansmit register xxxx xxxx uuuu uuuu 14h sspcon wcol sspo v sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 85h trisa por t a data direction register --11 1111 --11 1111 94h ssp- st a t d/ a p s r/ w u a bf --00 0000 --00 0000 legend: x = unkno wn, u = unchanged, - = unimplemented read as '0'. shaded cells are not used b y the ssp in spi mode . note 1: these bits are unimplemented, read as '0'.
pic16c72 series ? 1998 microchip technology inc. preliminary ds39016a -page 43 8.3 spi mode f or pic16cr72 this section contains register de nitions and oper a- tional char acter istics of the spi module on the pic16cr72 de vice o nly . additional inf or mation on spi oper ation ma y be f ound in the picmicro mid-range mcu ref erence man ual , ds33023. figure 8-4: ssp st a t : sync serial p or t status register (ad dress 94 h ) (pic16cr72) r/w -0 r/w -0 r-0 r-0 r-0 r-0 r-0 r-0 smp cke d/ a p s r/ w u a bf r = readab le bit w = wr itab le bit u = unimplemented bit, read as ? - n = v alue at por reset bit7 bit0 bit 7: s mp : spi data input sample phase spi ma ster op er ation 1 = input data sampled at end of data output time 0 = input data sampled at middle of data output time spi sla v e mode smp m ust be cleared when spi is used in sla v e mode bit 6: c ke : spi cloc k edge select ckp = 0 1 = data tr ansmitted on r ising edge of sck 0 = data tr ansmitted on f alling edge of sck ckp = 1 1 = data tr ansmitted on f alling edge of sck 0 = data tr ansmitted on r ising edge of sck bit 5: d / a : data/ address bit (i 2 c mode only) 1 = indicates that the last b yte receiv ed or tr ansmitted w as data 0 = indicates that the last b yte receiv ed or tr ansmitted w as address bit 4: p : stop bit (i 2 c mode only . this bit is cleared when the ssp module is disab led, or when the star t bit is detected last, sspen is cleared) 1 = indicates that a stop bit has been detected last (this bit is '0' on reset) 0 = stop bit w as not detected last bit 3: s : star t bit (i 2 c mode only . this bit is cleared when the ssp module is disab led, or when the stop bit is detected last, sspen is cleared) 1 = indicates that a star t bit has been detected last (this bit is '0' on reset) 0 = star t bit w as not detected last bit 2: r / w : read/wr ite bit inf or mation (i 2 c mode only) this bit holds the r/w bit inf or mation f ollo wing the last address match. this bit is only v alid from the address match to the ne xt star t bit, stop bit, or a ck bit. 1 = read 0 = wr ite bit 1: u a : update address (10-bit i 2 c mode only) 1 = indicates that the user needs to update the address in the ssp add register 0 = address does not need to be updated bit 0: b f : buff er full status bit receiv e (spi and i 2 c modes) 1 = receiv e complete , sspb uf is full 0 = receiv e not complete , sspb uf is empty t r ansmit (i 2 c mode only) 1 = t r ansmit in prog ress , sspb uf is full 0 = t r ansmit complete , sspb uf is empty
pic16c72 series ds39016a -page 44 preliminary ? 1998 microchip technology inc. figure 8-5: sspcon: sync serial p or t contr ol register (ad dress 14 h ) (pic16cr72) r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 wcol sspo v sspen ckp sspm3 sspm2 sspm1 sspm0 r = readab le bit w = wr itab le bit u = unimplemented bit, read as ? - n = v alue at por reset bit7 bit0 bit 7: w col : wr ite collision detect bit 1 = the sspb uf register is wr itten while it is still tr ansmitting the pre vious w ord (m ust be cleared in softw are) 0 = no collision bit 6: ssp o v : receiv e ov er o w indicator bit in spi mode 1 = a ne w b yte is receiv ed while the sspb uf register is still holding the pre vious data. in case of o v er- o w , the data in sspsr is lost. ov er o w can only occur in sla v e mode . the user m ust read the sspb uf , e v en if only tr ansmitting data, to a v oid setting o v er o w . in master o per ation , the o v er o w bit is not set since each ne w reception (and tr ansmission) is initiated b y wr iting to the sspb uf register . 0 = no o v er o w in i 2 c mode 1 = a b yte is receiv ed while the sspb uf register is still holding the pre vious b yte . sspo v is a "don? care" in tr ansmit mode . sspo v m ust be cleared in softw are in either mode . 0 = no o v er o w bit 5: ssp en : synchronous ser ial p or t enab le bit in spi mode 1 = enab les ser ial por t and con gures sck, sdo , and sdi as ser ial por t pins 0 = disab les ser ial por t and con gures these pins as i/o por t pins in i 2 c mode 1 = enab les the ser ial por t and con gures the sd a and scl pins as ser ial por t pins 0 = disab les ser ial por t and con gures these pins as i/o por t pins in both modes , when enab led, these pins m ust be proper ly con gured as input or output. bit 4: ck p : cloc k p olar ity select bit in spi mode 1 = idle state f or cloc k is a high le v el 0 = idle state f or cloc k is a lo w le v el in i 2 c mode sck release control 1 = enab le cloc k 0 = holds cloc k lo w (cloc k stretch) (used to ensure data setup time) bit 3-0: sspm 3:sspm0 : synchronous ser ial p or t mode select bits 0000 = spi master o per ation, cloc k = f osc /4 0001 = spi master o per ation, cloc k = f osc /16 0010 = spi master o per ation, cloc k = f osc /64 0011 = spi master o per ation, cloc k = tmr2 output/2 0100 = spi sla v e mode , cloc k = sck pin. ss pin control enab led. 0101 = spi sla v e mode , cloc k = sck pin. ss pin control disab led. ss can be used as i/o pin 0110 = i 2 c sla v e mode , 7-bit address 0111 = i 2 c sla v e mode , 10-bit address 1011 = i 2 c f ir mw are controlled master o per ation (sla v e idle) 1110 = i 2 c sla v e mode , 7-bit address with star t and stop bit interr upts enab led 1111 = i 2 c sla v e mode , 10-bit address with star t and stop bit interr upts enab led
pic16c72 series ? 1998 microchip technology inc. preliminary ds39016a -page 45 8.3.1 oper ation of ssp module in spi mode - pic16cr72 a b loc k diag r am of the ssp module in spi mode is sho wn in figure 8-6 . the spi mode allo ws 8-bits of data to be synchro- nously tr ansmitted and receiv ed sim ultaneously . t o accomplish comm unication, typically three pins are used: ser ial data out (sdo) rc5/sdo ser ial data in (sdi) rc4/sdi/sd a ser ial cloc k (sck) rc3/sck/scl additionally a f our th pin ma y be used when in a sla v e mode of oper ation: sla v e select ( ss ) ra5/ ss /an4 when initializing the spi, se v er al options need to be speci ed. this is done b y prog r amming the appropr iate control bits in the sspcon register (sspcon<5:0>) and sspst a t<7:6>. these control bits allo w the f ol- lo wing to be speci ed: ma ster op er ation (sck is the cloc k output) sla v e mode (sck is the cloc k input) cloc k p olar ity (idle state of sck) cloc k edge (output data on r ising/f alling edge of sck) cloc k rate (master o per ation only) sla v e select mode (sla v e mode only) t o enab le the ser ial por t, ssp enab le bit, sspen ( sspcon<5>) m ust be set. t o reset or recon gure spi mode , clear bit sspen, re-initializ e the sspcon reg- ister , and then set bit sspen. this con gures the sdi, sdo , sck, and ss pins as ser ial por t pins . f or the pins to beha v e as the ser ial por t function, the y m ust ha v e their data direction bits (in the trisc register) appro- pr iately prog r ammed. that is: sdi m ust ha v e trisc<4> set sdo m ust ha v e trisc<5> cleared sck (master o per ation) m ust ha v e trisc<3> cleared sck (sla v e mode) m ust ha v e trisc<3> set ss m ust ha v e trisa<5> set figure 8-6: ssp bloc k dia gram (spi mode)(pic16cr72) note: when the spi is in sla v e mode with ss pin control enab led, (sspcon<3:0> = 0100 ) the spi module will reset if the ss pin is set to v dd . note: if the spi is used in sla v e mode with cke = '1', then the ss pin control m ust be enab led. read wr ite inter nal data b us rc4/ sdi /sd a rc5/ sdo ra5/ s s /an4 rc3/ sck / sspsr reg sspb uf reg sspm3:sspm0 bit0 shift cloc k ss control enab le edge select cloc k select tmr2 output t cy prescaler 4, 16, 64 trisc<3> 2 edge select 2 4 scl
pic16c72 series ds39016a -page 46 preliminary ? 1998 microchip technology inc. t able 8-2 register s associated with spi operation (pic16cr72) ad dress name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 v alue on: por, bor v alue on all other resets 0bh,8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 (1) adif (1) (1) sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 (1) adie (1) (1) sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 87h trisc por tc data direction register 1111 1111 1111 1111 13h sspb uf synchronous ser ial p or t receiv e buff er/t r ansmit register xxxx xxxx uuuu uuuu 14h sspcon wcol sspo v sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 85h trisa por t a data direction register --11 1111 --11 1111 94h sspst a t smp cke d/ a p s r/ w u a bf 0000 0000 0000 0000 legend: x = unkno wn, u = unchanged, - = unimplemented read as '0'. shaded cells are not used b y the ssp in spi mode . note 1: a lw a ys maintain these bits clear .
pic16c72 series ? 1998 microchip technology inc. preliminary ds39016a -page 47 8.4 ssp i 2 c operation the ssp module in i 2 c mode fully implements all sla v e functions , e xcept gener al call suppor t, and pro vides interr upts on star t and stop bits in hardw are to f acilitate r mw are implementations of the master functions . the ssp module implements the standard mode speci ca- tions as w ell as 7-bit and 10-bit addressing. t w o pins are used f or data tr ansf er . these are the rc3/ sck/scl pin, which is the cloc k (scl), and the rc4/ sdi/sd a pin, which is the data (sd a). the user m ust con gure these pins as inputs or outputs through the trisc<4:3> bits . the ssp module functions are enab led b y setting ssp enab le bit sspen (sspcon<5>). figure 8-7: ssp bloc k dia gram (i 2 c mode) the ssp module has v e registers f or i 2 c oper ation. these are the: ssp control register (sspcon) ssp status register (sspst a t) ser ial receiv e/t r ansmit buff er (sspb uf) ssp shift register (sspsr) - not directly acces- sib le ssp address register (ssp add) the sspcon register allo ws control of the i 2 c oper a- tion. f our mode selection bits (sspcon<3:0>) allo w one of the f ollo wing i 2 c modes to be selected: i 2 c sla v e mode (7-bit address) i 2 c sla v e mode (10-bit address) i 2 c sla v e mode (7-bit address), with star t and stop bit interr upts enab led i 2 c sla v e mode (10-bit address), with star t and stop bit interr upts enab led i 2 c fir mw are controlled master o per ation, sla v e is idle selection of an y i 2 c mode , with the sspen bit set, f orces the scl and sd a pins to be open dr ain, pro- vided these pins are prog r ammed to inputs b y setting the appropr iate trisc bits . additional inf or mation on ssp i 2 c oper ation ma y be f ound in the picmicro mid-range mcu ref erence man ual , ds33023. 8.4.1 sla ve mode in sla v e mode , the scl and sd a pins m ust be con g- ured as inputs (trisc<4:3> set). the ssp module will o v err ide the input state with the output data when required (sla v e-tr ansmitter). when an address is matched or the data tr ansf er after an address match is receiv ed, the hardw are automati- cally will gener ate the ac kno wledge ( a ck ) pulse , and then load the sspb uf register with the receiv ed v alue currently in the sspsr register . there are cer tain conditions that will cause the ssp module not to giv e this a ck pulse . these are if either (or both): a) the b uff er full bit bf (sspst a t<0>) w as set bef ore the tr ansf er w as receiv ed. b) the o v er o w bit sspo v (sspcon<6>) w as set bef ore the tr ansf er w as receiv ed. in this case , the sspsr register v alue is not loaded into the sspb uf , b ut bit sspif (pir1<3>) is set. t ab le 8-3 sho ws what happens when a data tr ansf er b yte is receiv ed, giv en the status of bits bf and sspo v . the shaded cells sho w the condition where user softw are did not proper ly clear the o v er o w condi- tion. flag bit bf is cleared b y reading the sspb uf reg- ister while bit sspo v is cleared through softw are . the scl cloc k input m ust ha v e a minim um high and lo w f or proper oper ation. the high and lo w times of the i 2 c speci cation as w ell as the requirement of the ssp module is sho wn in timing par ameter #100 and par am- eter #101. read wr ite sspsr reg match detect ssp add reg star t and stop bit detect sspb uf reg inter nal data b us addr match set, reset s , p bits (sspst a t re g) rc3/sck /scl rc4/ shift cloc k ms b sd i/ lsb sd a
pic16c72 series ds39016a -page 48 preliminary ? 1998 microchip technology inc. 8.4.1.1 a ddressing once the ssp module has been enab led, it w aits f or a st ar t condition to occur . f ollo wing the st ar t condi- tion, the 8-bits are shifted into the sspsr register . all incoming bits are sampled with the r ising edge of the cloc k (scl) line . the v alue of register sspsr<7:1> is compared to the v alue of the ssp add register . the address is compared on the f alling edge of the eighth cloc k (scl) pulse . if the addresses match, and the bf and sspo v bits are clear , the f ollo wing e v ents occur : a) the sspsr register v alue is loaded into the sspb uf register . b) the b uff er full bit, bf is set. c) an a ck pulse is gener ated. d) ssp interr upt ag bit, sspif (pir1<3>) is set (interr upt is gener ated if enab led) - on the f alling edge of the ninth scl pulse . in 10-bit address mode , tw o address b ytes need to be receiv ed b y the sla v e . the v e most signi cant bits (msbs) of the rst address b yte specify if this is a 10-bit address . bit r/ w (sspst a t<2>) m ust specify a wr ite so the sla v e de vice will receiv e the second address b yte . f or a 10-bit address the rst b yte w ould equal 1111 0 a9 a8 0 ? where a9 and a8 are the tw o msbs of the address . the sequence of e v ents f or 10-bit address is as f ollo ws , with steps 7- 9 f or sla v e-tr ansmit- ter : 1. receiv e rst (high) b yte of address (bits sspif , bf , and bit u a (sspst a t<1>) are set). 2. update the ssp add register with second (lo w) b yte of address (clears bit u a and releases the scl line). 3. read the sspb uf register (clears bit bf) and clear ag bit sspif . 4. receiv e second (lo w) b yte of address (bits sspif , bf , and u a are set). 5. update the ssp add register with the rst (high) b yte of address , if match releases scl line , this will clear bit u a. 6. read the sspb uf register (clears bit bf) and clear ag bit sspif . 7. receiv e repeated st ar t condition. 8. receiv e rst (high) b yte of address (bits sspif and bf are set). 9. read the sspb uf register (clears bit bf) and clear ag bit sspif . t able 8-3 data t ransf er received byte actions status bits as data t ransf er is received sspsr ? sspb uf generate a ck pulse set bit sspif (ssp interrupt occur s if enab led) bf sspo v 0 0 y es y es y es 1 0 no no y es 1 1 no no y es 0 1 no no y es
pic16c72 series ? 1998 microchip technology inc. preliminary ds39016a -page 49 8.4.1.2 reception when the r/ w bit of the address b yte is clear and an address match occurs , the r/ w bit of the sspst a t register is cleared. the receiv ed address is loaded into the sspb uf register . when the address b yte o v er o w condition e xists , then no ac kno wledge ( a ck ) pulse is giv en. an o v er o w con- dition is de ned as either bit bf (sspst a t<0>) is set or bit sspo v (sspcon<6>) is set. an ssp interr upt is gener ated f or each data tr ansf er b yte . flag bit sspif (pir1<3>) m ust be cleared in soft- w are . the sspst a t register is used to deter mine the status of the b yte . figure 8-8: i 2 c w a vef orms f or reception (7-bit ad dress) p 9 8 7 6 5 d0 d1 d2 d3 d4 d5 d6 d7 s a7 a6 a5 a4 a3 a2 a1 sd a scl 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 bus master ter minates tr ansf er bit s spo v is set because the sspb uf register is still full. cleared in softw are sspb uf register is read a ck receiving data receiving data d0 d1 d2 d3 d4 d5 d6 d7 a ck r/ w =0 receiving address sspif (pir1<3>) bf (sspst a t<0>) sspo v (sspcon<6>) a ck a ck is not sent.
pic16c72 series ds39016a -page 50 preliminary ? 1998 microchip technology inc. 8.4.1.3 tr ansmission when the r/ w bit of the incoming address b yte is set and an address match occurs , the r/ w bit of the sspst a t register is set. the receiv ed address is loaded into the sspb uf register . the a ck pulse will be sent on the ninth bit, and pin rc3/sck/scl is held lo w . the tr ansmit data m ust be loaded into the ssp- b uf register , which also loads the sspsr register . then pin rc3/sck/scl should be enab led b y setting bit ckp (sspcon<4>). the master m ust monitor the scl pin pr ior to asser ting another cloc k pulse . the sla v e de vices ma y be holding off the master b y stretch- ing the cloc k. the eight data bits are shifted out on the f alling edge of the scl input. this ensures that the sd a signal is v alid dur ing the scl high time ( figure 8-9 ). an ssp interr upt is gener ated f or each data tr ansf er b yte . flag bit sspif m ust be cleared in softw are , and the sspst a t register is used to deter mine the status of the b yte . flag bit sspif is set on the f alling edge of the ninth cloc k pulse . as a sla v e-tr ansmitter , the a ck pulse from the master- receiv er is latched on the r ising edge of the ninth scl input pulse . if the sd a line w as high (not a ck ), then the data tr ansf er is complete . when the a ck is latched b y the sla v e , the sla v e logic is reset (resets sspst a t reg- ister) and the sla v e then monitors f or another occur- rence of the st ar t bit. if the sd a line w as lo w ( a ck ), the tr ansmit data m ust be loaded into the sspb uf reg- ister , which also loads the sspsr register . then pin rc3/sck/scl should be enab led b y setting bit ckp . figure 8-9: i 2 c w a vef orms f or t ransmission (7-bit ad dress) sd a scl sspif (pir1<3>) bf (sspst a t<0>) ckp (sspcon<4>) a7 a6 a5 a4 a3 a2 a1 a ck d7 d6 d5 d4 d3 d2 d1 d0 a ck t r ansmitting data r/ w = 1 receiving address 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 p cleared in softw are sspb uf is wr itten in softw are f rom ssp i nterr upt ser vice routine set bit after wr iting to sspb uf s data in sampled scl held lo w while cpu responds to sspif (the sspb uf m ust be wr itten-to bef ore the ckp bit can be set)
pic16c72 series ? 1998 microchip technology inc. preliminary ds39016a -page 51 8.4.2 ma ster op er ation master oper ation is suppor ted in r mw are using inter- r upt gener ation on the detection of the st ar t and st op conditions . the st op (p) and st ar t (s) bits are cleared from a reset or when the ssp module is disab led. the st op (p) and st ar t (s) bits will toggle based on the st ar t and st op conditions . control of the i 2 c b us ma y be tak en when the p bit is set, or the b us is idle and both the s and p bits are clear . in master oper ation , the scl and sd a lines are manip- ulated in r mw are b y clear ing the corresponding trisc<4:3> bit(s). the output le v el is alw a ys lo w , irre- spectiv e of the v alue(s) in por tc<4:3>. so when tr ansmitting data, a '1' data bit m ust ha v e the trisc<4> bit set (input) and a '0' data bit m ust ha v e the trisc<4> bit cleared (output). the same scenar io is tr ue f or the scl line with the trisc<3> bit. the f ollo wing e v ents will cause ssp interr upt flag bit, sspif , to be set (ssp interr upt if enab led): st ar t condition st op condition data tr ansf er b yte tr ansmitted/receiv ed ma ster oper ation c an be done with either the sla v e mode idle (sspm3:sspm0 = 1011 ) or with the sla v e activ e . when both master oper ation a nd sla v e modes are used, the softw are needs to diff erentiate the source(s) of the interr upt. f or more inf or mation on master oper ation, see an554 - softw are implementation of i 2 c bus master . 8.4.3 multi- ma ster op er ation in m ulti-master oper ation, t he interr upt gener ation on the detection of the st ar t and st op conditions allo ws the deter mination of when the b us is free . the st op (p) and st ar t (s) bits are cleared from a reset or when the ssp module is disab led. the st op (p) and st ar t (s) bits will toggle based on the st ar t and st op conditions . control of the i 2 c b us ma y be tak en when bit p (sspst a t<4>) is set, or the b us is idle and both the s and p bits clear . when the b us is b usy , enab ling the ssp interr upt will gener ate the interr upt when the st op condition occurs . in m ulti-master o per ation, the sd a line m ust be moni- tored to see if the signal le v el is the e xpected output le v el. this chec k only needs to be done when a high le v el is output. if a high le v el is e xpected and a lo w le v el is present, the de vice needs to release the sd a and scl lines (set trisc<4:3>). there are tw o stages where this arbitr ation can be lost, these are: address t r ansf er data t r ansf er when the sla v e logic is enab led, the sla v e contin ues to receiv e . if arbitr ation w as lost dur ing the address tr ans- f er stage , comm unication to the de vice ma y be in prog ress . if addressed an a ck pulse will be gener ated. if arbitr ation w as lost dur ing the data tr ansf er stage , the de vice will need to re-tr ansf er the data at a later time . f or more inf or mation on master oper ation, see an578 - use of the ssp module in the of i 2 c multi-master en vironment . t able 8-4 r egister s associated with i 2 c operation ad dress name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 v alue on por, bor v alue on al l o ther resets 0bh, 8bh, 10bh,18bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 (1) adif (1) (1) sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 (1) adie (1) (1) sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 13h sspb uf synchronous ser ial p or t receiv e buff er/t r ansmit register xxxx xxxx uuuu uuuu 93h ssp add synchronous ser ial p or t (i 2 c mode) address register 0000 0000 0000 0000 14h sspcon wcol sspo v sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 94h sspst a t smp (2) cke (2) d/ a p s r/ w u a bf 0000 0000 0000 0000 87h t risc por tc data direction register 1111 1111 1111 1111 legend: x = unkno wn, u = unchanged, - = unimplemented locations read as '0'. shaded cells are not used b y ssp module in spi mode . note 1: these bits are unimplemented, read as '0'. 2: the smp and cke bits are implemented on the pic16c r72 only . on the pic16c72, these tw o bits are unimplemented, read as '0'.
pic16c72 series ds39016a -page 52 preliminary ? 1998 microchip technology inc. notes:
pic16c72 series ? 1998 microchip technology inc. preliminary ds39016a -page 53 9.0 analog-to-digital con ver ter (a/d) module the analog-to-digital (a/d) con v er ter module has v e inputs f or the pic16c72 /r72 . the a/d allo ws con v ersion of an analog input signal to a corresponding 8-bit digital n umber (ref er to applica- tion note an546 f or use of a/d con v er ter). the output of the sample and hold is the input into the con v er ter , which gener ates the result via successiv e appro xima- tion. the analog ref erence v oltage is softw are select- ab le to either the de vice s positiv e supply v oltage ( v dd ) or the v oltage le v el on the ra3/an3/ v ref pin. the a/d con v er ter has a unique f eature of being ab le to oper ate while the de vice is in sleep mode . t o oper- ate in sleep , the a/d con v ersion cloc k m ust be der iv ed from the a/d s inter nal rc oscillator . additional inf or mation on the a/d module is a v ailab le in the picmicro mid-range mcu ref erence man ual , ds33023. the a/d module has three registers . these registers are: a/d result register ( adres) a/d control register 0 ( adcon0) a/d control register 1 (adcon1) a de vice reset f orces all registers to their reset state . this f orces the a/d module to be tur ned off , and an y con v ersion is abor ted. the adcon0 register , sho wn in figure 9-1 , controls the oper ation of the a/d module . the adcon1 regis- ter , sho wn in figure 9-2 , con gures the functions of the por t pins . the por t pins can be con gured as analog inputs (ra3 can also be a v oltage ref erence) or as dig- ital i/o . figure 9-1: adcon0 register (ad dress 1f h ) r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 u-0 r/w -0 adcs1 adcs0 chs2 chs1 chs0 go/ done adon r = readab le bit w = wr itab le bit u = unimplemented bit, read as ? - n = v alue at por reset bit7 bit0 bit 7-6: adcs1:adcs0: a/d con v ersion cloc k select bits 00 = f osc /2 01 = f osc /8 10 = f osc /32 11 = f rc (cloc k der iv ed from an inter nal rc oscillator) bit 5-3: chs2:chs0 : analog channel select bits 000 = channel 0, (ra0/an0) 001 = channel 1, (ra1/an1) 010 = channel 2, (ra2/an2) 011 = channel 3, (ra3/an3) 100 = channel 4, (ra5/an4) bit 2: go/ done : a/d con v ersion status bit if adon = 1 1 = a/d con v ersion in prog ress (setting this bit star ts the a/d con v ersion) 0 = a/d con v ersion not in prog ress (this bit is automatically cleared b y hardw are when the a/d con v er- sion is complete) bit 1: unimplemented : read as '0' bit 0: adon : a/d on bit 1 = a/d con v er ter module is oper ating 0 = a/d con v er ter module is shutoff and consumes no oper ating current
pic16c72 series ds39016a -page 54 preliminary ? 1998 microchip technology inc. figure 9-2: adcon1 register (ad dress 9f h ) u-0 u-0 u-0 u-0 u-0 r/w -0 r/w -0 r/w -0 pcf g2 pcfg1 pcfg0 r = readab le bit w = wr itab le bit u = unimplemented bit, read as ? - n = v alue at por reset bit7 bit0 bit 7-3: unimplemented: read as '0' bit 2-0: pcfg2:pcfg0 : a/d p or t con gur ation control bits a = analog input d = digital i/o pcfg2:pcfg0 ra0 ra1 ra2 ra5 ra3 v ref 000 a a a a a v dd 001 a a a a v ref ra3 010 a a a a a v dd 011 a a a a v ref ra3 100 a a d d a v dd 101 a a d d v ref ra3 11x d d d d d gnd
pic16c72 series ? 1998 microchip technology inc. preliminary ds39016a -page 55 the adres register contains the result of the a/d con- v ersion. when the a/d con v ersion is complete , the result is loaded into the adres register , the go/ done bit (adcon0<2>) is cleared, and a/d interr upt ag bit adif is set. the b loc k diag r am of the a/d module is sho wn in figure 9-3 . the v alue that is in the adres register is not modi ed f or a p o w er-on reset. the adres register will contain unkno wn data after a p o w er-on reset. after the a/d module has been con gured as desired, the selected channel m ust be acquired bef ore the con- v ersion is star ted. the analog input channels m ust ha v e their corresponding tris bits selected as an input. t o deter mine acquisition time , see section 9.1 . after this acquisition time has elapsed the a/d con v er- sion can be star ted. the f ollo wing steps should be f ol- lo w ed f or doing an a/d con v ersion: 1. con gu re the a/d module: con gure analog pins / v oltage ref erence / and digital i/o (adcon1) select a/d input channel (adcon0) select a/d con v ersion cloc k (adcon0) t ur n on a/d module (adcon0) 2. con gure a/d i nterr upt (if desired): clear adif bit set adie bit set gie bit 3. w ait the required acquisition time . 4. star t con v ersion: set go/ done bit (adcon0) 5. w ait f or a/d con v ersion to complete , b y either : p olling f or the go/ done bit to be cleared or w aiting f or the a/d interr upt 6. read a/d result register (adres), clear bit adif if required. 7. f or ne xt con v ersion, go to step 1 or step 2 as required. the a/d con v ersion time per bit is de ned as t ad . a minim um w ait of 2 t ad is required bef ore ne xt acquisition star ts . figure 9-3: a/d bloc k dia gram (input v oltage) v a in v ref (ref erence v oltage) v dd pcfg 2:pcfg0 chs 2 : chs 0 000 or 010 or 100 001 or 011 or 101 ra5/an4 ra3/an3/ v ref ra2/an2 ra1/an1 ra0/an0 100 011 010 001 000 a/d con v er ter
pic16c72 series ds39016a -page 56 preliminary ? 1998 microchip technology inc. 9.1 a/d acquisition requirements f or the a/d con v er ter to meet its speci ed accur acy , the charge holding capacitor ( c hold ) m ust be allo w ed to fully charge to the input channel v oltage le v el. the analog input model is sho wn in figure 9-4 . the source impedance ( r s ) and the inter nal sampling s witch ( r ss ) impedance directly aff ect the time required to charge the capacitor c hold . the sampling s witch ( r ss ) impedance v ar ies o v er the de vice v oltage ( v dd ). the source impedance aff ects the offset v oltage at the ana- log input (due to pin leakage current). the maxim um recommended impedance f or analog sour ces is 10 k w . after the analog input channel is selected (changed) this acquisition m ust be done bef ore the con v ersion can be star ted. t o calculate the minim um acquisition time , t acq , see the picmicro mid-range mcu ref erence man ual , ds33023. t his equation calculates the acquisition time to within 1/2 lsb error (512 steps f or the a/d). the 1/2 lsb error is the maxim um error allo w ed f or the a/d to meet its speci ed accur acy . figure 9-4: analog inp ut model c pin v a rs anx 5 pf v dd v t = 0.6v v t = 0.6v i leakage r ic 1k sampling switch ss r ss c hold = d a c capacitance v ss 6v sampling switch 5v 4 v 3v 2v 5 6 7 8 9 10 11 ( k w ) v dd = 51.2 pf 500 na legend c pin v t i leakage r ic ss c hold = input capacitance = threshold v oltage = leakage current at the pin due to = interconnect resistance = sampling s witch = sample/hold capacitance (from d a c) v ar ious junctions
pic16c72 series ? 1998 microchip technology inc. preliminary ds39016a -page 57 9.2 selecting the a /d con ver sion cloc k the a/d con v ersion time per bit is de ned as t ad . the a/d con v ersion requires 9.5 t ad per 8-bit con v ersion. t he source of the a/d con v ersion cloc k is softw are selectab le . the f our possib le options f or t ad are: 2 t osc 8 t osc 32 t osc inter nal rc oscillator f or correct a/d con v ersions , the a/d con v ersion cloc k ( t ad ) m ust be selected to ensure a minim um t ad time of 1.6 m s . t ab le 9-1 sho ws the resultant t ad times der iv ed from the de vice oper ating frequencies and the a/d cloc k source selected. 9.3 conf iguring analog p or t pins the adcon1, trisa, and trise registers control the oper ation of the a/d por t pins . the por t pins that are desired as analog inputs m ust ha v e their correspond- ing tris bits set (input). if the tris bit is cleared (out- put), the digital output le v el ( v oh or v ol ) will be con v er ted. the a/d oper ation is independent of the state of the chs2:chs0 bits and the tris bits . t able 9-1 t ad vs . de vice operating frequencies note 1: when reading the por t register , all pins con gured as analog input channels will read as cleared (a lo w le v el). pins con g- ured as digital inputs , will con v er t an ana- log input. analog le v els on a digitally con gured input will not aff ect the con v er- sion accur acy . note 2: analog le v els on an y pin that is de ned as a digital input (including the a n4:an0 pins), ma y cause the input b uff er to con- sume current that is out of the de vices speci cation. ad cloc k sour ce ( t ad ) de vice frequenc y operation adcs1:adcs0 20 mhz 5 mhz 1.25 mhz 333.33 khz 2 t osc 00 100 ns (2) 400 ns (2) 1.6 m s 6 m s 8 t osc 01 400 ns (2) 1.6 m s 6.4 m s 24 m s (3) 32 t osc 10 1.6 m s 6.4 m s 25.6 m s (3) 96 m s (3) rc (5) 11 2 - 6 m s (1,4) 2 - 6 m s (1,4) 2 - 6 m s (1,4) 2 - 6 m s (1) legend: shaded cells are outside of recommended r ange . note 1: the rc source has a typical t ad time of 4 m s . 2: these v alues violate the minim um required t ad time . 3: f or f aster con v ersion times , the selection of another cloc k source is recommended. 4: when de vice frequency is g reater than 1 mhz, the rc a/d con v ersion cloc k source is recommended f or sleep oper ation only . 5: f or e xtended v oltage de vices (lc), please ref er to electr ical speci cations section.
pic16c72 series ds39016a -page 58 preliminary ? 1998 microchip technology inc. 9.4 a/d con ver sions 9.5 use of the ccp t rig g er an a/d con v ersion can be star ted b y the ?pecial e v ent tr igger of the ccp1 modul e . this requires that the ccp1m3:ccp1m0 bits (ccp1con<3:0>) be pro- g r ammed as 1011 and that the a/d module is enab led (adon bit is set). when the tr igger occurs , the go/ done bit will be set, star ting the a/d con v ersion, and the timer1 counter will be reset to z ero . timer1 is reset to automatically repeat the a/d acquisition per iod with minimal softw are o v erhead (mo ving the adres to the desired location). the appropr iate analog input channel m ust be selected and the minim um acquisition done bef ore the ?pecial e v ent tr igger sets the go/ done bit (star ts a con v ersion). if the a/d module is not enab led (adon is cleared), then the ?pecial e v ent tr igger will be ignored b y the a/d module , b ut will still reset the timer1 counter . t able 9-2 register s/bits associated with a/d note: the go/ done bit should no t be set in the same instr uction that tur ns on the a/d . ad dress name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 v alue on: por, bor v alue on all other resets 0bh,8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 adif sspif ccp1if tmr2if tmr1if -0-- 0000 -0-- 0000 8ch pie1 adie sspie ccp1ie tmr2ie tmr1ie -0-- 0000 -0-- 0000 1eh adres a/d result register xxxx xxxx uuuu uuuu 1fh adcon0 adcs1 adcs0 chs2 chs1 chs0 go/ done adon 0000 00-0 0000 00-0 9fh adcon1 pcfg2 pcfg1 pcfg0 ---- -000 ---- -000 05h por t a ra5 ra4 ra3 ra2 ra1 ra0 --0x 0000 --0u 0000 85h trisa por t a data direction register --11 1111 --11 1111 legend: x = unkno wn, u = unchanged, - = unimplemented read as '0'. shaded cells are not used f or a/d con v ersion.
pic16c72 series ? 1998 microchip technology inc. preliminary ds39016a -page 59 10.0 special features of the cpu the pic16c72 ser ies has a host of such f eatures intended to maximiz e system reliability , minimiz e cost through elimination of e xter nal components , pro vide po w er sa ving oper ating modes and off er code protec- tion. these are: oscillator selection reset - p o w er-on reset (por) - p o w er-up timer (pwr t) - oscillator star t-up timer (ost) - bro wn-out reset (bor) interr upts w atchdog timer (wdt) sleep code protection id locations in- c ircuit s er ial p rog r amming the pic16cx x x f amily has a w atchdog timer which can be shut off only through con gur ation bits . it r uns off its o wn rc oscillator f or added reliability . there are tw o timers that off er necessar y dela ys on po w er-up . one is the oscillator star t-up timer (ost), intended to k eep the chip in reset until the cr ystal oscillator is sta- b le . the other is the p o w er-up timer (pwr t), which pro vides a x ed dela y of 72 ms (nominal) on po w er-up only , designed to k eep the par t in reset while the po w er supply stabiliz es . with these tw o timers on-chip , most applications need no e xter nal reset circuitr y . sleep mode is designed to off er a v er y lo w current po w er-do wn mode . the user can w ak e-up from sleep through e xter nal reset, w atchdog timer w ak e-up , or through an interr upt. se v er al oscillator options are also made a v ailab le to allo w the par t to t the application. the rc oscillator option sa v es system cost while the lp cr ystal option sa v es po w er . a set of con gur ation bits are used to select v ar ious options . additional inf or mation on special f eatures is a v ailab le in the picmicro mid-range mcu f amily ref erence man ual , ds33023. 10.1 c on guration bits the con gur ation bits can be prog r ammed (read as '0') or left unprog r ammed (read as '1') to select v ar ious de vice con gur ations . these bits are mapped in pro- g r am memor y location 2007h. the user will note that address 2007h is be y ond the user prog r am memor y space . in f act, it belongs to the special test/con gur ation memor y space (2000h - 3fffh), which can be accessed only dur ing prog r am- ming. figure 10-1: configuration w or d f or pic16c72/r72 cp1 cp0 cp1 cp0 cp1 cp0 boden cp1 cp0 pwr te wdte fosc1 fosc0 register : config address 2007h bit13 bit0 bit 13-8 cp1:cp0 : code protection bits (2) 5-4 : 11 = code protection off 10 = upper half of prog r am memor y code protected 01 = upper 3/4th of prog r am memor y code protected 00 = all memor y is code protected bit 7: unimplemented : read as '1' bit 6: boden : bro wn-out reset enab le bit (1) 1 = bor enab led 0 = bor disab led bit 3: pwr te : p o w er-up timer enab le bit (1) 1 = pwr t disab led 0 = pwr t enab led bit 2: wdte : w atchdog timer enab le bit 1 = wdt enab led 0 = wdt disab led bit 1-0: fosc1:fosc0 : oscillator selection bits 11 = rc oscillator 10 = hs oscillator 01 = xt oscillator 00 = lp oscillator note 1: enab ling bro wn-out reset automatically enab les p o w er-up timer (pwr t) regardless of the v alue of bit pwr te . ensure the p o w er-up timer is enab led an ytime bro wn-out reset is enab led. 2: all of the cp1:cp0 pairs ha v e to be giv en the same v alue to enab le the code protection scheme listed.
pic16c72 series ds39016a -page 60 preliminary ? 1998 microchip technology inc. 10.2 oscillator con gurations 10.2.1 oscillator t ypes the pic16cx x x f amily can be oper ated in f our diff er- ent oscillator modes . the user can prog r am tw o con g- ur ation bits (fosc1 and fosc0) to select one of these f our modes: lp lo w p o w er cr ystal xt cr ystal/resonator hs high speed cr ystal/resonator rc resistor/capacitor 10.2.2 cr ystal oscillator/ceramic resonators in xt , lp or hs modes a cr ystal or cer amic resonator is connected to the osc1/clkin and osc2/clk out pins to estab lish oscillation ( figure 10-2 ). the pic16cxxx f amily oscillator design requires the use of a par allel cut cr ystal. use of a ser ies cut cr ystal ma y giv e a frequency out of the cr ystal man uf acturers spec- i cations . when in xt , lp or hs modes , the de vice can ha v e an e xter nal cloc k source to dr iv e the osc1/ clkin pin ( figure 10-3 ). figure 10-2: cr ystal/ceramic resonator operation (hs, xt or lp osc configuration) figure 10-3: external cloc k input operation (hs, xt or lp osc configuration) t able 10-1 ceramic resonator s t able 10-2 capacitor selection f or cr ystal oscillator note 1: see t ab le 10-1 and t ab le 10-2 f or recom- mended v alues of c1 and c2 . 2: a ser ies resistor (rs) ma y be required f or a t str ip cut cr ystals . 3: rf v ar ies with the cr ystal chosen. c1 (1) c2 (1) xt al osc2 osc1 rf (3) sleep t o logic pic16cxx x rs (2) i nter nal osc1 osc2 open cloc k from e xt. system pic16cx x x rang es t ested: mode freq osc1 osc2 xt 455 khz 2.0 mhz 4.0 mhz 68 - 100 pf 15 - 68 pf 15 - 68 pf 68 - 100 pf 15 - 68 pf 15 - 68 pf hs 8.0 mhz 16.0 mhz 10 - 68 pf 10 - 22 pf 10 - 68 pf 10 - 22 pf these v alues are f or design guidance onl y . see notes at bottom of page . resonator s used: 455 khz p anasonic efo-a455k04b 0.3% 2.0 mhz mur ata er ie csa2.00mg 0.5% 4.0 mhz mur ata er ie csa4.00mg 0.5% 8.0 mhz mur ata er ie csa8.00mt 0.5% 16.0 mhz mur ata er ie csa16.00mx 0.5% all resonators used did not ha v e b uilt-in capacitors . osc t ype cr ystal freq cap. rang e c1 cap. rang e c2 lp 32 khz 33 pf 33 pf 200 khz 15 pf 15 pf xt 200 khz 47-68 pf 47-68 pf 1 mhz 15 pf 15 pf 4 mhz 15 pf 15 pf hs 4 mhz 15 pf 15 pf 8 mhz 15-33 pf 15-33 pf 20 mhz 15-33 pf 15-33 pf these v alues are f or design guidance onl y . see notes at bottom of page . cr ystals used 32 khz epson c-001r32.768k-a 20 ppm 200 khz std xtl 200.000khz 20 ppm 1 mhz ecs ecs-10-13-1 50 ppm 4 mhz ecs ecs-40-20-1 50 ppm 8 mhz epson ca-301 8.000m-c 30 ppm 20 mhz epson ca-301 20.000m-c 30 ppm note 1: recommended v alues of c1 and c2 are identical to the r anges tested ( t ab le 10-1 ). 2: higher capacitance increases the stability of oscillator b ut also increases the star t-up time . 3: since each resonator/cr ystal has its o wn char acter istics , the user should consult the resonator/cr ystal man uf acturer f or appropr i- ate v alues of e xter nal components . 4: rs ma y be required in hs mode as w ell as xt mode to a v oid o v erdr iving cr ystals with lo w dr iv e le v el speci cation.
pic16c72 series ? 1998 microchip technology inc. preliminary ds39016a -page 61 10.2.3 rc oscillator f or timing insensitiv e applications the ?c de vice option off ers additional cost sa vings . the rc oscillator frequency is a function of the supply v oltage , the resis- tor ( r ext ) and capacitor ( c ext ) v alues , and the oper at- ing temper ature . in addition to this , the oscillator frequency will v ar y from unit to unit due to nor mal pro- cess par ameter v ar iation. fur ther more , the diff erence in lead fr ame capacitance betw een pac kage types will also aff ect the oscillation frequency , especially f or lo w c ext v alues . the user also needs to tak e into account v ar iation due to toler ance of e xter nal r and c compo- nents used. figure 10-4 sho ws ho w the r/c combina- tion is connected to the pic16cxxx f amily . figure 10-4: rc oscillator mode 10.3 reset the pic16cx x x f amily diff erentiates betw een v ar ious kinds of reset: p o w er-on reset (por) mclr reset dur ing nor mal oper ation mclr reset dur ing sleep wdt reset (nor mal oper ation) bro wn-out reset (bor) some registers are not aff ected in an y reset condition; their status is unkno wn on por and unchanged in an y other reset. most other registers are reset to a ?eset state on p o w er-on reset (por), on the mclr and wdt reset, on mclr reset dur ing sleep , and bro wn- out reset (bor). the y are not aff ected b y a wdt w ak e-up , which is vie w ed as the resumption of nor mal oper ation. the t o and pd bits are set or cleared diff er- ently in diff erent reset situations as indicated in t ab le 10-4 . these bits are used in softw are to deter- mine the nature of the reset. see t ab le 10-6 f or a full descr iption of reset states of all registers . a simpli ed b loc k diag r am of the on-chip reset circuit is sho wn in figure 10-5 . the pic16c72/cr72 ha v e a mclr noise lter in the mclr reset path. the lter will detect and ignore small pulses . it should be noted that a wdt reset does not dr iv e mclr pin lo w . osc2/clkout cext rext pic16cxxx osc1 fosc/4 internal clock v dd v ss recommended values: 3 k w re xt 100 k w ce xt > 20pf
pic16c72 series ds39016a -page 62 preliminary ? 1998 microchip technology inc. figure 10-5: simplified bloc k dia gram of on-c hip reset cir cuit s r q exter nal reset mclr v dd osc1 wdt module v dd r ise detect ost/pwr t on-chi p rc osc wdt time-out p o w er-on reset ost 10 -b it ripple counter pwr t chip_reset 10 -b it ripple counter r eset enab le ost enab le pwr t sleep note 1: this is a separ ate oscillator from the rc oscillator of the clkin pin. bro wn-out reset boden (1)
pic16c72 series ? 1998 microchip technology inc. preliminary ds39016a -page 63 10.4 p o wer -on reset (por) a p o w er-on reset pulse is gener ated on-chip when v dd r ise is detected (in the r ange of 1.5 v - 2.1v). t o tak e adv antage of the por, just tie the mclr pin directly (or through a resistor) to v dd . this will eliminate e xter nal rc components usually needed to create a p o w er-on reset. a maxim um r ise time f or v dd is spec- i ed. see electr ical speci cations f or details . f or a slo w r ise time , see figure 10-6 . when the de vice star ts nor mal oper ation (e xits the reset condition), de vice oper ating par ameters (v oltage , frequency , temper ature ,...) m ust be met to ensure oper- ation. if these conditions are not met, the de vice m ust be held in reset until the oper ating conditions are met. bro wn-out reset ma y be used to meet the star tup con- ditions . figure 10-6: external p o wer -on reset cir cuit (f or slo w v dd p o wer -up) 10.5 p o wer -up timer (pwr t) the p o w er-up timer pro vides a x ed 72 ms nominal time-out on po w er-up only , from the por. the p o w er- up timer oper ates on an inter nal rc oscillator . the chip is k ept in reset as long as the pwr t is activ e . the pwr t s time dela y allo ws v dd to r ise to an acceptab le le v el. a con gur ation bit is pro vided to enab le/disab le the pwr t . the po w er-up time dela y will v ar y from chip to chip due to v dd , temper ature , and process v ar iation. see dc par ameters f or details . 10.6 oscillator star t-up timer (ost) the oscillator star t-up timer (ost) pro vides 1024 oscillator cycle (from osc1 input) dela y after the pwr t dela y is o v er . this ensures that the cr ystal oscil- lator or resonator has star ted and stabiliz ed. the ost time-out is in v ok ed only f or xt , lp and hs modes and only on p o w er-on reset or w ak e-up from sleep . 10.7 br o wn-out reset (bor) a con gur ation bit, boden, can disab le (if clear/pro- g r ammed) or enab le (if set) the bro wn-out reset cir- cuitr y . if v dd f alls belo w 4.0v (3.8v - 4.2v r ange) f or g reater than par ameter #35, the bro wn-out situation will reset the chip . a reset ma y not occur if v dd f alls belo w 4.0v f or less than par ameter #35. the chip will remain in bro wn-out reset until v dd r ises abo v e bv dd . the p o w er-up timer will no w be in v ok ed and will k eep the chip in reset an additional 72 ms . if v dd drops belo w bv dd while the p o w er-up timer is r unning, the chip will go bac k into a bro wn-out reset and the p o w er-up timer will be initializ ed. once v dd r ises abo v e bv dd , the p o w er-up timer will e x ecute a 72 ms time dela y . the p o w er-up timer should alw a ys be enab led when bro wn-out reset is enab led. note 1: exter nal p o w er-on reset circuit is required only if v dd po w er-up slope is too slo w . the diode d helps discharge the capacitor quic kly when v dd po w ers do wn. 2: r < 40 k w is recommended to mak e sure that v oltage drop across r does not violate the de vice s electr ical speci cation. 3: r1 = 100 w to 1 k w will limit an y current o wing into mclr from e xter nal capacitor c in the e v ent of mclr/ v pp pin break- do wn due to electrostatic discharge (esd) or electr ical ov erstress (eos). c r1 r d v dd mclr pic16cx x x
pic16c72 series ds39016a -page 64 preliminary ? 1998 microchip technology inc. 10.8 time-out sequence on po w er-up the time-out sequence is as f ollo ws: first pwr t time-out is in v ok ed after the por time dela y has e xpired. then ost is activ ated. the total time-out will v ar y based on oscillator con gur ation and the status of the pwr t . f or e xample , in rc mode with the pwr t disab led, there will be no time-out at all. figure 10-7 , figure 10-8 , figure 10-9 and figure 10-10 depict time- out sequences on po w er-up . since the time-outs occur from the por pulse , if mclr is k ept lo w long enough, the time-outs will e xpire . then br inging mclr high will begin e x ecution immediately ( figure 10-9 ). this is useful f or testing pur poses or to synchroniz e more than one pic16cx x x f amily de vice oper ating in par allel. t ab le 10-5 sho ws the reset conditions f or some special function registers , while t ab le 10-6 sho ws the reset conditions f or all the registers . 10.9 p o wer contr ol/status register (pcon) the p o w er control/status register , pcon has up to tw o bits , depending upon the de vice . bit0 is bro wn-out reset status bit, bor . bit bor is unkno wn o n a p o w er-on reset. it m ust then be set b y the user and chec k ed on subsequent resets to see if bit bor cleared, indicating a bor occurred. the bor bit is a "don? care" bit and is not necessar ily predictab le if the bro wn-out reset circuitr y is disab led (b y clear ing bit boden in the con gur ation w ord). bit1 is por (p o w er-on reset status bit) . it is cleared on a p o w er-on reset and unaff ected otherwise . the user m ust set this bit f ollo wing a p o w er-on reset. t able 10-3 time-out in v arious situations t able 10-4 status bits and their significance t able 10-5 reset condition f or s pecial register s oscillator con gura- tion p o wer -up br o wn-out w ake-up fr om sleep pwr te = 0 pwr te = 1 xt , hs , lp 72 ms + 1024 t osc 1024 t osc 72 ms + 1024t osc 1024 t osc rc 72 ms 72 ms por bor t o pd 0 x 1 1 p o w er-on reset 0 x 0 x illegal, t o is set on por 0 x x 0 illegal, pd is set on por 1 0 x x bro wn-out reset 1 1 0 1 wdt reset 1 1 0 0 wdt w ak e-up 1 1 u u mclr reset dur ing nor mal oper ation 1 1 1 0 mclr reset dur ing sleep or interr upt w ak e-up from sleep condition pr ogram counter st a tus register pcon register p o w er-on reset 000h 0001 1xxx ---- --0x mclr reset dur ing nor mal oper ation 000h 000u uuuu ---- --uu mclr reset dur ing sleep 000h 0001 0uuu ---- --uu wdt reset 000h 0000 1uuu ---- --uu wdt w ak e-up pc + 1 uuu0 0uuu ---- --uu bro wn-out reset 000h 0001 1uuu ---- --u0 interr upt w ak e-up from sleep pc + 1 (1) uuu1 0uuu ---- --uu legend: u = unchanged, x = unkno wn, - = unimplemented bit read as '0' . note 1: when the w ak e-up is due to an interr upt and the gie bit is set, the pc is loaded with the interr upt v ector (0004h).
pic16c72 series ? 1998 microchip technology inc. preliminary ds39016a -page 65 t able 10-6 initialization conditions f or all register s register p o wer -on reset, br o wn-out reset mclr resets wdt reset w ake-up via wdt o r i nter - rupt w xxxx xxxx uuuu uuuu uuuu uuuu indf n/a n/a n/a tmr0 xxxx xxxx uuuu uuuu uuuu uuuu pcl 0000h 0000h pc + 1 (2) st a tus 0001 1xxx 000q quuu (3) uuuq quuu (3) fsr xxxx xxxx uuuu uuuu uuuu uuuu por t a --0x 0000 --0u 0000 --uu uuuu por tb xxxx xxxx uuuu uuuu uuuu uuuu por tc xxxx xxxx uuuu uuuu uuuu uuuu pcla th ---0 0000 ---0 0000 ---u uuuu intcon 0000 000x 0000 000u uuuu uuuu (1) pir1 -0-- 0000 -0-- 0000 -u-- uuuu (1) tmr1l xxxx xxxx uuuu uuuu uuuu uuuu tmr1h xxxx xxxx uuuu uuuu uuuu uuuu t1con --00 0000 --uu uuuu --uu uuuu tmr2 0000 0000 0000 0000 uuuu uuuu t2con -000 0000 -000 0000 -uuu uuuu sspb uf xxxx xxxx uuuu uuuu uuuu uuuu sspcon 0000 0000 0000 0000 uuuu uuuu ccpr1l xxxx xxxx uuuu uuuu uuuu uuuu ccpr1h xxxx xxxx uuuu uuuu uuuu uuuu ccp1con --00 0000 --00 0000 --uu uuuu adres xxxx xxxx uuuu uuuu uuuu uuuu adcon0 0000 00-0 0000 00-0 uuuu uu-u option 1111 1111 1111 1111 uuuu uuuu trisa --11 1111 --11 1111 --uu uuuu trisb 1111 1111 1111 1111 uuuu uuuu trisc 1111 1111 1111 1111 uuuu uuuu pie1 -0-- 0000 -0-- 0000 -u-- uuuu pcon ---- --0u ---- --uu ---- --uu pr2 1111 1111 1111 1111 1111 1111 ssp add 0000 0000 0000 0000 uuuu uuuu sspst a t --00 0000 --00 0000 --uu uuuu adcon1 ---- -000 ---- -000 ---- -uuu legend: u = unchanged, x = unkno wn, - = unimplemented bit, read as '0', q = v alue depends on condition note 1: one or more bits in intcon, pir1 and/or pir2 will be aff ected (to cause w ak e-up). 2: when the w ak e-up is due to an interr upt and the gie bit is set, the pc is loaded with the interr upt v ector (0004h). 3: see t ab le 10-5 f or reset v alue f or speci c condition.
pic16c72 series ds39016a -page 66 preliminary ? 1998 microchip technology inc. figure 10-7: time-out sequence on p o wer -up ( mclr tied to v dd ) figure 10-8: time-out sequence on p o wer -up ( mclr not tied to v dd ): case 1 figure 10-9: time-out sequence on p o wer -up ( mclr not tied to v dd ): case 2 t pwrt t ost v dd mclr internal por pwr t time-out ost time-out internal reset t pwrt t ost v dd mclr internal por pwr t time-out ost time-out internal reset v dd mclr internal por pwr t time-out ost time-out internal reset t pwrt t ost
pic16c72 series ? 1998 microchip technology inc. preliminary ds39016a -page 67 figure 10-10: slo w rise time ( mclr tied to v dd ) v dd mclr internal por pwr t time-out ost time-out internal reset 0v 1v 5v t pwrt t ost
pic16c72 series ds39016a -page 68 preliminary ? 1998 microchip technology inc. 10.10 interrupts the pic16c72/cr72 has 8 sources of interr upt. the interr upt control register (intcon) records individual interr upt requests in ag bits . it also has individual and global interr upt enab le bits . a global interr upt enab le bit, gie (intcon<7>) enab les (if set) all un-mask ed interr upts or disab les (if cleared) all interr upts . when bit gie is enab led, and an interr upt s ag bit and mask bit are set, the interr upt will v ector immediately . individual interr upts can be dis- ab led through their corresponding enab le bits in v ar i- ous registers . individual interr upt bits are set regardless of the status of the gie bit. the gie bit is cleared on reset. the ?etur n from interr upt instr uction, retfie , e xits the interr upt routine as w ell as sets the gie bit, which re-enab les interr upts . the rb0/int pin interr upt, the rb por t change inter- r upt and the tmr0 o v er o w interr upt ags are con- tained in the intcon register . the per ipher al interr upt ags are contained in the spe- cial function registers pir1 and pir2. the correspond- ing interr upt enab le bits are contained in special function registers pie1 and pie2, and the per ipher al interr upt enab le bit is contained in special function reg- ister intcon. when an interr upt is responded to , the gie bit is cleared to disab le an y fur ther interr upt, the retur n address is pushed onto the stac k and the pc is loaded with 0004h. once in the interr upt ser vice routine the source(s) of the interr upt can be deter mined b y polling the interr upt ag bits . the interr upt ag bit(s) m ust be cleared in softw are bef ore re-enab ling interr upts to a v oid recursiv e interr upts . f or e xter nal interr upt e v ents , such as the int pin or por tb change interr upt, the interr upt latency will be three or f our instr uction cycles . the e xact latency depends when the interr upt e v ent occurs . the latency is the same f or one or tw o cycle instr uctions . individual interr upt ag bits are set regardless of the status of their corresponding mask bit or the gie bit 10.10.1 int interr upt exter nal interr upt on rb0/int pin is edge tr iggered: either r ising if bit intedg (option<6>) is set, or f all- ing, if the intedg bit is clear . when a v alid edge appears on the rb0/int pin, ag bit intf (intcon<1>) is set. this interr upt can be disab led b y clear ing enab le bit inte (intcon<4>). flag bit intf m ust be cleared in softw are in the interr upt ser vice rou- tine bef ore re-enab ling this interr upt. the int interr upt can w ak e-up the processor from sleep , if bit inte w as set pr ior to going into sleep . the status of global inter- r upt enab le bit gie decides whether or not the proces- sor br anches to the interr upt v ector f ollo wing w ak e-up . see section 10.13 f or details on sleep mode . 10.10.2 tmr0 interr upt an o v er o w (ffh ? 00h) in the tmr0 register will set ag bit t0if (intcon<2>). the interr upt can be enab led/disab led b y setting/clear ing enab le bit t0ie (intcon<5>). ( section 4.0 ) 10.10.3 p or tb intcon change an input change on por tb<7:4> sets ag bit rbif (intcon<0>). the interr upt can be enab led/disab led b y setting/clear ing enab le bit rbie (intcon<4>). ( section 3.2 ) figure 10-11: interrupt logic note: individual interr upt ag bits are set regard- less of the status of their corresponding mask bit or the gie bit. adi f adi e sspi f sspi e ccp1i f ccp1i e tmr2i f tmr2i e tmr1i f tmr1i e t0 if t0 ie intf inte rbif rbie gie peie w ak e - up (if in sleep mode) interr upt to cpu clear gie bit
pic16c72 series ? 1998 microchip technology inc. preliminary ds39016a -page 69 10.11 conte xt sa ving during interrupts dur ing an interr upt, only the retur n pc v alue is sa v ed on the stac k. t ypically , users ma y wish to sa v e k e y reg- isters dur ing an interr upt, i.e ., w register and st a tus register . this will ha v e to be implemented in softw are . example 10-1 stores and restores the w and st a tus registers . the register , w_temp , m ust be de ned in each bank and m ust be de ned at the same offset from the bank base address (i.e ., if w_temp is de ned at 0x20 in bank 0, it m ust also be de ned at 0xa0 in bank 1). the e xample: a) stores the w register . b) stores the st a tus register in bank 0 . c) e x ecutes the isr code . d) restores the st a tus register (and bank select bit). e) restores the w register . example 10-1: sa ving st a tus, w , and pcla th register s in ram movwf w_temp ; copy w to w_temp register, could be bank one or zero swapf status,w ; swap status to be saved into w clrf status ; bank 0, regardless of current bank, clears irp,rp1,rp0 movwf status_temp ; save status to bank zero status_temp registe r : : interr upt ser vice routine (isr) - user def ined : swapf status_temp,w ; swap status_temp register into w ;(sets bank to original state) movwf status ; move w into status register swapf w_temp,f ; swap w_temp swapf w_temp,w ; swap w_temp into w
pic16c72 series ds39016a -page 70 preliminary ? 1998 microchip technology inc. 10.12 w atc hdog timer (wdt) the w atchdog timer is as a free r unning on-chip rc oscillator which does not require an y e xter nal compo- nents . this rc oscillator is separ ate from the rc oscil- lator of the osc1/clkin pin. that means that the wdt will r un, e v en if the cloc k on the osc1/clkin and osc2/clk out pins of the de vice has been stopped, f or e xample , b y e x ecution of a sleep instr uction. dur ing nor mal oper ation, a wdt time-out gener ates a de vice reset (w atchdog timer reset). if the de vice is in sleep mode , a wdt time-out causes the de vice to w ak e-up and contin ue with nor mal oper ation (w atch- dog timer w ak e-up). the t o bit in the st a tus register will be cleared upon a w atchdog timer time-out. the wdt can be per manently disab led b y clear ing con gur ation bit wdte ( section 10.1 ). wdt time-out per iod v alues ma y be f ound in the elec- tr ical speci cations section under par ameter #31. v al- ues f or the wdt prescaler (actually a postscaler , b ut shared with the timer0 prescaler) ma y be assigned using the option_reg register . . figure 10-12: w atc hdog timer bloc k dia gram figure 10-13: summar y of w atc hdog timer register s note: the clrwdt and sleep instr uctions clear the wdt and the postscaler , if assigned to the wdt , and pre v ent it from timing out and gener ating a de vice reset condition. note: when a clrwdt instr uction is e x ecuted and the prescaler is assigned to the wdt , the prescaler count will be cleared, b ut the prescaler assignment is not changed. ad dress name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2007h con g. bits (1) boden (1) cp1 cp0 pwr te (1) wdte fosc1 fosc0 81h,181h option rbpu intedg t0cs t0se psa ps2 ps1 ps0 legend: shaded cells are not used b y the w atchdog timer . note 1: see figure 10-1 f or oper ation of these bits . f rom tmr0 cloc k source ( figure 4-2 ) t o tmr0 ( figure 4-2 ) p ostscaler wdt timer wdt enab le bit 0 1 m u x psa 8 - to - 1 mux ps2:ps0 0 1 mux psa wdt time-out note: psa and ps2:ps0 are bits in the option register . 8
pic16c72 series ? 1998 microchip technology inc. preliminary ds39016a -page 71 10.13 p o wer -do wn mode (sleep) p o w er-do wn mode is entered b y e x ecuting a sleep instr uction. if enab led, the w atchdog timer will be cleared b ut k eeps r unning, the pd bit (st a tus<3>) is cleared, the t o (st a tus<4>) bit is set, and the oscillator dr iv er is tur ned off . the i/o por ts maintain the status the y had, bef ore the sleep instr uction w as e x ecuted (dr iving high, lo w , or hi-impedance). f or lo w est current consumption in this mode , place all i/o pins at either v dd , or v ss , ensure no e xter nal cir- cuitr y is dr a wing current from the i/o pin, po w er-do wn the a/d , disab le e xter nal cloc ks . pull all i/o pins , that are hi-impedance inputs , high or lo w e xter nally to a v oid s witching currents caused b y oating inputs . the t0cki input should also be at v dd or v ss f or lo w est current consumption. the contr ib ution from on-chip pull-ups on por tb should be considered. the mclr pin m ust be at a logic high le v el ( v ihmc ). 10.13.1 w ak e-up from sleep the de vice can w ak e up from sleep through one of the f ollo wing e v ents: 1. exter nal reset input on mclr pin. 2. w atchdog timer w ak e-up (if wdt w as enab led). 3. interr upt from int pin, rb por t change , or some p er ipher al interr upts . exter nal mclr reset will cause a de vice reset. all other e v ents are considered a contin uation of prog r am e x ecution and cause a "w ak e-up". the t o and pd bits in the st a tus register can be used to deter mine the cause of de vice reset. the pd bit, which is set on po w er-up , is cleared when sleep is in v ok ed. the t o bit is cleared if a wdt time-out occurred (and caused w ak e-up). the f ollo wing per ipher al interr upts can w ak e the de vice from sleep: 1. tmr1 interr upt. timer1 m ust be oper ating as an asynchronous counter . 2. ssp (star t/stop) bit detect interr upt. 3. ssp tr ansmit or receiv e in sla v e mode (spi/i 2 c). 4. ccp capture mode interr upt. 5. a/d con v ersion (when a/d cloc k source is rc). 6. special e v ent tr igger (timer1 in asynchronous mode using an e xter nal cloc k). other per ipher als cannot gener ate interr upts since dur- ing sleep , no on-chip cloc ks are present. when the sleep instr uction is being e x ecuted, the ne xt instr uction (pc + 1) is pre-f etched. f or the de vice to w ak e-up through an interr upt e v ent, the corresponding interr upt enab le bit m ust be set (enab led). w ak e-up is regardless of the state of the gie bit. if the gie bit is clear (disab led), the de vice contin ues e x ecution at the instr uction after the sleep instr uction. if the gie bit is set (enab led), the de vice e x ecutes the instr uction after the sleep instr uction and then br anches to the inter- r upt address (0004h). in cases where the e x ecution of the instr uction f ollo wing sleep is not desir ab le , the user should ha v e a nop after the sleep instr uction. 10.13.2 w ak e-up using interr upts when global interr upts are disab led (gie cleared) and an y interr upt source has both its interr upt enab le bit and interr upt ag bit set, one of the f ollo wing will occur : if the interr upt occurs bef ore the e x ecution of a sleep instr uction, the sleep instr uction will com- plete as a nop . theref ore , the wdt and wdt postscaler will not be cleared, the t o bit will not be set and pd bits will not be cleared. if the interr upt occurs during or after the e x ecu- tion of a sleep instr uction, the de vice will immedi- ately w ak e up from sleep . the sleep instr uction will be completely e x ecuted bef ore the w ak e-up . theref ore , the wdt and wdt postscaler will be cleared, the t o bit will be set and the pd bit will be cleared. ev en if the ag bits w ere chec k ed bef ore e x ecuting a sleep instr uction, it ma y be possib le f or f lag bits to become set bef ore the sleep instr uction completes . t o deter mine whether a sleep instr uction e x ecuted, test the pd bit. if the pd bit is set, the sleep instr uction w as e x ecuted as a nop . t o ensure that the wdt is cleared, a clrwdt instr uc- tion should be e x ecuted bef ore a sleep instr uction.
pic16c72 series ds39016a -page 72 preliminary ? 1998 microchip technology inc. figure 10-14: w ake-up fr om sleep t hr ough interrupt 10.14 pr ogram v eri cation/code pr otection if the code protection bit(s) ha v e not been pro- g r ammed, the on-chip prog r am memor y can be read out f or v er i cation pur poses . 10.15 id locations f our memor y locations (2000h - 2003h) are designated as id locations where the user can store chec ksum or other code-identi cation n umbers . these locations are not accessib le dur ing nor mal e x ecution b ut are read- ab le and wr itab le dur ing prog r am/v er ify . it is recom- mended that only the 4 least signi cant bits of the id location are used. f or r om de vices , these v alues are submitted along with the r om code . 10.16 in-cir cuit serial pr ogramming pic16cxxx f amily microcontrollers can be ser ially prog r ammed while in the end application circuit. this is simply done with tw o lines f or cloc k and data, and three other lines f or po w er , g round, and the prog r amming v oltage . this allo ws customers to man uf acture boards with unprog r ammed de vices , and then prog r am the microcontroller just bef ore shipping the product. this also allo ws the most recent r mw are or a custom r m- w are to be prog r ammed. f or complete details of ser ial prog r amming, please ref er to the in-circuit ser ial prog r amming (icsp) guide , ds30277. q1 q2 q3 q4 q1 q2 q3 q4 q1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 clk out(4) int pin intf ag (intcon<1>) gie bit (intcon<7>) instr uction flo w pc instr uction f etched instr uction e x ecuted pc pc+1 pc+2 inst(pc) = sleep inst(pc - 1) inst(pc + 1) sleep processor in sleep interr upt latency (note 2) inst(pc + 2) inst(pc + 1) inst(0004h) inst(0005h) inst(0004h) dumm y cycle pc + 2 0004h 0005h dumm y cycle t ost (2) pc+2 note 1: xt , hs or lp oscillator mode assumed. 2: t ost = 1024 t osc (dr a wing not to scale) this dela y will not be there f or rc osc mode . 3: gie = '1' assumed. in this case after w ak e- up , the processor jumps to the interr upt routine . if gie = '0', e x ecution will contin ue in-line . 4: clk out is not a v ailab le in these osc modes , b ut sho wn here f or timing ref erence . note: microchip does not recommend code pro- tecting windo w ed de vices .
pic16c72 series ? 1998 microchip technology inc. preliminary ds39016a -page 73 11.0 instruction set summar y each pic16cxxx f amily instr uction is a 14-bit w ord divided into an opcode which speci es the instr uc- tion type and one or more oper ands which fur ther spec- ify the oper ation of the instr uction. the pic16cxx x f amily instr uction set summar y in t ab le 11-2 lists b yte- oriented , bit-oriented , and literal and contr ol oper a- tions . t ab le 11-1 sho ws the opcode eld descr iptions . f or b yte-oriented instr uctions , 'f' represents a le reg- ister designator and 'd' represents a destination desig- nator . the le register designator speci es which le register is to be used b y the instr uction. the destination designator speci es where the result of the oper ation is to be placed. if 'd' is z ero , the result is placed in the w register . if 'd' is one , the result is placed in the le register speci ed in the instr uction. f or bit-oriented instr uctions , 'b' represents a bit eld designator which selects the n umber of the bit aff ected b y the oper ation, while 'f' represents the n umber of the le in which the bit is located. f or literal and contr ol oper ations , 'k' represents an eight or ele v en bit constant or liter al v alue . t able 11-1 op code field descriptions the instr uction set is highly or thogonal and is g rouped into three basic categor ies: byte-oriented oper ations bit-oriented oper ations literal and contr ol oper ations all instr uctions are e x ecuted within one single instr uc- tion cycle , unless a conditional test is tr ue or the pro- g r am counter is changed as a result of an instr uction. in this case , the e x ecution tak es tw o instr uction cycles with the second cycle e x ecuted as a nop . one instr uc- tion cycle consists of f our oscillator per iods . thus , f or an oscillator frequency of 4 mhz, the nor mal instr uction e x ecution time is 1 m s . if a conditional test is tr ue or the prog r am counter is changed as a result of an instr uc- tion, the instr uction e x ecution time is 2 m s . t ab le 11-2 lists the instr uctions recogniz ed b y the mp asm assemb ler . figure 11-1 sho ws the gener al f or mats that the instr uc- tions can ha v e . all e xamples use the f ollo wing f or mat to represent a he xadecimal n umber : 0xhh where h signi es a he xadecimal digit. figure 11-1: general fo rmat f or instructions a descr iption of each instr uction is a v ailab le in the pic- micro mid-range mcu f amily ref erence man ual, ds33023. field description f register le address (0x00 to 0x7f) w w or king register (accum ulator) b bit address within an 8-bit le register k liter al eld, constant data or label x don't care location (= 0 or 1) the assemb ler will gener ate code with x = 0. it is the recommended f or m of use f or compatibility with all microchip softw are tools . d destination select; d = 0: store result in w , d = 1: store result in le register f . def ault is d = 1 pc prog r am counter to time-out bit pd p o w er-do wn bit note: t o maintain upw ard compatibility with future pic16cxxx products , do not use the option and tris instr uctions . byte-oriented le register oper ations 13 8 7 6 0 d = 0 f or destination w opcode d f (file #) d = 1 f or destination f f = 7-bit le register address bit-oriented le register oper ations 13 10 9 7 6 0 opcode b (bit #) f (file #) b = 3-bit bit address f = 7-bit le register address literal and contr ol oper ations 13 8 7 0 opcode k ( liter al) k = 8-bit immediate v alue 13 11 10 0 opcode k ( liter al) k = 11-bit immediate v alue gener al call and goto instr uctions only
pic16c72 series ds39016a -page 74 preliminary ? 1998 microchip technology inc. t able 11-2 pic16cxxx instruction set mnemonic, operands description cyc les 14-bit opcode status aff ected notes msb lsb byte-oriented file register opera tions add wf and wf clrf clr w comf decf decfsz incf incfsz ior wf mo vf mo vwf nop rlf rrf subwf sw apf xor wf f , d f , d f - f , d f , d f , d f , d f , d f , d f , d f - f , d f , d f , d f , d f , d add w and f and w with f clear f clear w complement f decrement f decrement f , skip if 0 increment f increment f , skip if 0 inclusiv e or w with f mo v e f mo v e w to f no oper ation rotate left f through carr y rotate right f through carr y subtr act w from f sw ap nib b les in f exclusiv e or w with f 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff c ,dc ,z z z z z z z z z c c c ,dc ,z z 1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2 1,2 1,2 1,2 1,2 1,2 bit -oriented file register opera tions bcf bsf btfsc btfss f , b f , b f , b f , b bit clear f bit set f bit t est f , skip if clear bit t est f , skip if set 1 1 1 (2) 1 (2) 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff 1,2 1,2 3 3 literal and contr ol opera tions addl w andl w call clr wdt go t o iorl w mo vl w retfie retl w return sleep subl w xorl w k k k - k k k - k - - k k add liter al and w and liter al with w call subroutine clear w atchdog timer go to address inclusiv e or liter al with w mo v e liter al to w retur n from interr upt retur n with liter al in w retur n from subroutine go into standb y mode subtr act w from liter al exclusiv e or liter al with w 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk c ,dc ,z z t o , pd z t o , pd c ,dc ,z z note 1: when an i/o register is modi ed as a function of itself ( e .g., movf portb, 1 ), the v alue used will be that v alue present on the pins themselv es . f or e xample , if the data latch is '1' f or a pin con gured as input and is dr iv en lo w b y an e xter nal de vice , the data will be wr itten bac k with a '0'. 2: if this instr uction is e x ecuted on the tmr0 register (and, where applicab le , d = 1), the prescaler will be cleared if assigned to the timer0 module . 3: if prog r am counter (pc) is modi ed or a conditional test is tr ue , the instr uction requires tw o cycles . the second cycle is e x ecuted as a nop .
pic16c72 series ? 1998 microchip technology inc. preliminary ds39016a -page 75 12.0 de velopment suppor t 12.1 de velopme nt t ools the picmicr o? microcontrollers are suppor ted with a full r ange of hardw are and softw are de v elopment tools: picmaster a /picmaster ce real-time in-circuit em ulator icepic ? lo w-cost pic16c5x and pic16cxxx in-circuit em ulator pr o ma te a ii univ ersal prog r ammer picst ar t a plus entr y-le v el prototype prog r ammer picdem-1 lo w-cost demonstr ation board picdem-2 lo w-cost demonstr ation board picdem-3 lo w-cost demonstr ation board mp asm assemb ler mplab ? sim softw are sim ulator mplab-c 17 (c compiler) fuzzy logic de v elopment system ( fuzzy tech a - mp) a descr iption of each de v elopment tool is a v ailab le in the midr ange ref erence man ual, ds33023. 12.2 picdem-2 lo w-cost pic16cxx demonstration boar d the picdem-2 is a simple demonstr ation board that suppor ts the pic16c62, pic16c64, pic16c65, pic16c73 and pic16c74 microcon trollers . all the necessar y hardw are and softw are is included to r un the basic demonstr ation prog r ams . the user can prog r am the sample microcontrollers pro vided with the picdem-2 board, on a pr o ma te ii pro- g r ammer or picst ar t -plus , and easily test r mw are . the picmaster em ulator ma y also be used with the picdem-2 board to test r mw are . additional prototype area has been pro vided to the user f or adding addi- tional hardw are and connecting it to the microcontroller soc k et(s). some of the f eatures include a rs-232 inter- f ace , push-b utton s witches , a potentiometer f or sim u- lated analog input, a ser ial eepr om to demonstr ate usage of the i 2 c b us and separ ate headers f or connec- tion to an lcd module and a k e ypad.
pic16c72 series ds39016a -page 76 preliminary ? 1998 microchip technology inc. notes:
pic16c72 series ? 1998 microchip technology inc. preliminary ds39016a -page 77 13.0 e lectrical characteristics - pic16c72 series absolute maxim um ratings ? p arameter pic16c72 pic16cr72 ambient temper ature under bias -55 to +125?c -55 to +125?c stor age temper ature -65?c to +150?c -65?c to +150?c v oltage on an y pin with respect to v ss (e xcept v dd , mclr , and ra4) -0.3v to ( v dd + 0.3v) -0.3v to ( v dd + 0.3v) v oltage on v dd with respect to v ss -0.3 to +7.5v tbd v oltage on mclr with respect to v ss (note 1) -0.3 to +14v tbd v oltage on ra4 with respect to vss -0.3 to +14v tb d t otal po w er dissipation (note 2) 1.0w 1.0w maxim um current out of v ss pin 300 ma 300 ma maxim um current into v dd pin 250 ma 250 ma input clamp current, i ik ( v i < 0 or v i > v dd ) 20 ma 20 ma output clamp current, iok (v o < 0 or v o > v dd ) 20 ma 20 ma maxim um output current sunk b y an y i/o pin 25 ma 25 ma maxim um output current sourced b y an y i/o pin 25 ma 25 ma maxim um current sunk b y por t a and por tb (combined) 200 ma 200 ma maxim um current sourced b y por t a and por tb (combined) 200 ma 200 ma maxim um current sunk b y por tc 200 ma 200 ma maxim um current sourced b y por tc 200 ma 200 ma 1. v oltage spik es belo w v ss at the mclr pin, inducing currents g reater than 80 ma, ma y cause latch-up . thus , a ser ies resistor of 50-100 w should be used when applying a ?o w le v el to the mclr pin r ather than pulling this pin directly to v ss . 2. p o w er dissipation is calculated as f ollo ws: pdis = v dd x { i dd - ? i oh } + ? {( v dd - v oh ) x i oh } + ? ( v o l x i ol ). ? no tice: stresses abo v e those listed under ?bsolute maxim um ratings ma y cause per manent damage to the de vice . this is a stress r ating only and functional oper ation of the de vice at those or an y other conditions abo v e those indicated in the oper ation list- ings of this speci cation is not implied. exposure to maxim um r ating conditions f or e xtended per iods ma y aff ect de vice reliability .
pic16c72 series ds39016a -page 78 preliminary ? 1998 microchip technology inc. t able 13-1 cr oss ref erence of de vice specs (pic16c72) f or oscillator configurations and frequencies of operation (commer cial de vices ) t able 13-2 cr oss ref erence of de vice specs (pic16cr72) f or oscillator configurations and frequencies of operation (commer cial de vices ) osc pic16c72-04 pic16c72-10 pic16c72-20 pic16lc72-04 jw de vices rc v dd : 4.0v to 6.0v i dd : 5 ma max. at 5.5v i pd : 16 m a max. at 4v f req: 4 mhz max. v dd : 4.5v to 5.5v i dd : 2.7 ma typ . at 5.5v i pd : 1.5 m a typ . at 4v f req: 4 mhz max. v dd : 4.5v to 5.5v i dd : 2.7 ma typ . at 5.5v i pd : 1.5 m a typ . at 4v f req: 4 mhz max. v dd : 2.5v to 6.0v i dd : 3.8 m a max. at 3.0v i pd : 5.0 m a max. at 3v f req: 4 mhz max. v dd : 4.0v to 6.0v i dd : 5 ma max. at 5.5v i pd : 16 m a max. at 4v f req: 4 mhz max. xt v dd : 4.0v to 6.0v i dd : 5 ma max. at 5.5v i pd : 16 m a max. at 4v f req: 4 mhz max. v dd : 4.5v to 5.5v i dd : 2.7 ma typ . at 5.5v i pd : 1.5 m a typ . at 4v f req: 4 mhz max. v dd : 4.5v to 5.5v i dd : 2.7 ma typ . at 5.5v i pd : 1.5 m a typ . at 4v f req: 4 mhz max. v dd : 2.5v to 6.0v i dd : 3.8 m a max. at 3.0v i pd : 5.0 m a max. at 3v f req: 4 mhz max. v dd : 4.0v to 6.0v i dd : 5 ma max. at 5.5v i pd : 16 m a max. at 4v f req: 4 mhz max. hs v dd : 4.5v to 5.5v v dd : 4.5v to 5.5v v dd : 4.5v to 5.5v not recommended f or use in hs mode v dd : 4.5v to 5.5v i dd : 13.5 ma typ . at 5.5v i dd : 10 ma max. at 5.5v i dd : 20 ma max. at 5.5v i dd : 20 ma max. at 5.5v i pd : 1.5 m a typ . at 4.5v i pd : 1.5 m a typ . at 4.5v i pd : 1.5 m a typ . at 4.5v i pd : 1.5 m a typ . at 4.5v f req: 4 mhz max. f req: 10 mhz max. f req: 20 mhz max. f req: 20 mhz max. lp v dd : 4.0v to 6.0v i dd : 52.5 m a typ . at 32 khz, 4.0v i pd : 0.9 m a typ . at 4.0v f req: 200 khz max. not recommended f or use in lp mode not recommended f or use in lp mode v dd : 2.5v to 6.0v i dd : 48 m a max. at 32 khz, 3.0v i pd : 5.0 m a max. at 3.0v f req: 200 khz max. v dd : 2.5v to 6.0v i dd : 48 m a max. at 32 khz, 3.0v i pd : 5.0 m a max. at 3.0v f req: 200 khz max. the shaded sections indicate oscillator selections which are tested f or functionality , b ut not f or min/max speci cations . it is recommended that the user select the de vice type that ensures the speci cations required. osc pic16c r 72-04 pic16c r 72-10 pic16c r 72-20 pic16lc r 72-04 jw de vices rc v dd : 4.0v to 5.5v i dd : 5 ma max. at 5.5v i pd : 16 m a max. at 4v f req: 4 mhz max. v dd : 4.5v to 5.5v i dd : 2.7 ma typ . at 5.5v i pd : 1.5 m a typ . at 4v f req: 4 mhz max. v dd : 4.5v to 5.5v i dd : 2.7 ma typ . at 5.5v i pd : 1.5 m a typ . at 4v f req: 4 mhz max. v dd : 2.5v to 5.5v i dd : 3.8 ma max. at 3.0v i pd : 5.0 m a max. at 3v f req: 4 mhz max. v dd : 4.0v to 5.5v i dd : 5 ma max. at 5.5v i pd : 16 m a max. at 4v f req: 4 mhz max. xt v dd : 4.0v to 5.5v i dd : 5 ma max. at 5.5v i pd : 16 m a max. at 4v f req: 4 mhz max. v dd : 4.5v to 5.5v i dd : 2.7 ma typ . at 5.5v i pd : 1.5 m a typ . at 4v f req: 4 mhz max. v dd : 4.5v to 5.5v i dd : 2.7 ma typ . at 5.5v i pd : 1.5 m a typ . at 4v f req: 4 mhz max. v dd : 2.5v to 5.5v i dd : 3.8 ma max. at 3.0v i pd : 5.0 m a max. at 3v f req: 4 mhz max. v dd : 4.0v to 5.5v i dd : 5 ma max. at 5.5v i pd : 16 m a max. at 4v f req: 4 mhz max. hs v dd : 4.5v to 5.5v v dd : 4.5v to 5.5v v dd : 4.5v to 5.5v not recommended f or use in hs mode v dd : 4.5v to 5.5v i dd : 13.5 ma typ . at 5.5v i dd : 10 ma max. at 5.5v i dd : 20 ma max. at 5.5v i dd : 20 ma max. at 5.5v i pd : 1.5 m a typ . at 4.5v i pd : 1.5 m a typ . at 4.5v i pd : 1.5 m a typ . at 4.5v i pd : 1.5 m a typ . at 4.5v f req: 4 mhz max. f req: 10 mhz max. f req: 20 mhz max. f req: 20 mhz max. lp v dd : 4.0v to 5.5v i dd : 52.5 m a typ . at 32 khz, 4.0v i pd : 0.9 m a typ . at 4.0v f req: 200 khz max. not recommended f or use in lp mode not recommended f or use in lp mode v dd : 2.5v to 5.5v i dd : 48 m a max. at 32 khz, 3.0v i pd : 5.0 m a max. at 3.0v f req: 200 khz max. v dd : 2.5v to 5.5v i dd : 48 m a max. at 32 khz, 3.0v i pd : 5.0 m a max. at 3.0v f req: 200 khz max. the shaded sections indicate oscillator selections which are tested f or functionality , b ut not f or min/max speci cations . it is recommended that the user select the de vice type that ensures the speci cations required.
pic16c72 series ? 1998 microchip technology inc. preliminary ds39016a -page 79 13.1 dc characteristics: pic16c72/cr72-04 (commer cial, industrial, extended ) pic16c72/cr72-10 (commer cial, industrial, extended ) pic16c72/cr72-20 (commer cial, industrial, extended ) dc chara cteristics standard oper ating conditions (unless otherwise stated) oper ating temper ature -40?c t a +125?c f or e xtended , -40?c t a +85?c f or industr ial and 0?c t a +70?c f or commercial p aram no. characteristic sym pic16c72 pic16cr72 units conditions min t yp? max min t yp? max d001 d001a supply v oltage v dd 4.0 4.5 - - 6.0 5.5 4.0 4.5 - - 5.5 5.5 v v xt , rc and lp osc hs osc d002* ram data retention v oltage (note 1) v dr - 1.5 - - 1.5 - v d003 v dd star t v oltage to ensure inter nal p o w er- on reset signal v por - v ss - - v ss - v see section on p o w er- on reset f or details d004* v dd r ise r ate to ensure inter nal p o w er-on reset signal s vdd 0.05 - - 0.05 - - v/ms see section on p o w er- on reset f or details d005 bro wn-out reset v olt- age bvdd 3.7 4.0 4.3 3.7 4.0 4.3 v boden bit in con gur a- tion w ord enab led 3.7 4.0 4.4 3.7 4.0 4.4 v extended only d010 supply current (note 2,5) i dd - 2.7 5.0 - 2.7 5.0 ma xt , rc osc f osc = 4 mhz, v dd = 5.5v (note 4) d013 - 10 20 - 10 20 ma hs osc f osc = 20 mhz, v dd = 5.5v d015 bro wn-out reset current (note 6) d ibor - 350 425 - 350 425 m a bor enab led, v dd = 5.0v d020 p o w er-do wn current (note 3,5) i pd - 10.5 42 - 10.5 42 m a v dd = 4.0v , wdt enab led, -40 c to +85 c d021 - 1.5 16 - 1.5 16 m a v dd = 4.0v , wdt dis- ab led, -0 c to +70 c d021a - 1.5 19 - 1.5 19 m a v dd = 4.0v , wdt dis- ab led, -40 c to +85 c d021b - 2.5 19 - 2.5 19 m a v dd = 4.0v , wdt dis- ab led, -40 c to +125 c d023 bro wn-out reset current (note 6) d ibor - 350 425 - 350 425 m a bor enab led v dd = 5.0v * these par ameters are char acter iz ed b ut not tested. ? data in "t yp" column is at 5v , 25?c unless otherwise stated. these par ameters are f or design guidance only and are not tested. note 1: this is the limit to which v dd can be lo w ered without losing ram data. note 2: the supply current is mainly a function of the oper ating v oltage and frequency . other f actors such as i/o pin loading and s witching r ate , oscillator type , inter nal code e x ecution patter n, and temper ature also ha v e an impact on the current con- sumption. the test conditions f or all i dd measurements in activ e oper ation mode are: osc1 = e xter nal square w a v e , from r ail to r ail; all i/o pins tr istated, pulled to v dd mclr = v dd ; wdt enab led/disab led as speci ed. note 3: the po w er-do wn current in sleep mode does not depend on the oscillator type . p o w er-do wn current is measured with the par t in sleep mode , with all i/o pins in hi-impedance state and tied to v dd and v ss . note 4: f or rc osc con gur ation, current through re xt is not included. the current through the resistor can be estimated b y the f or m ula ir = v dd /2re xt (ma) with re xt in kohm. note 5: timer1 oscillator (when enab led) adds appro ximately 20 m a to the speci cation. this v alue is from char acter ization and is f or design guidance only . this is not tested. note 6: the d current is the additional current consumed when this per ipher al is enab led. this current should be added to the base i dd or i pd measurement.
pic16c72 series ds39016a -page 80 preliminary ? 1998 microchip technology inc. 13.2 dc characteristics: pic16lc72/lcr72-04 (commer cial, industrial) dc chara cteristics standard oper ating conditions (unless otherwise stated) oper ating temper ature -40?c t a +85?c f or industr ial and 0?c t a +70?c f or commercial p aram no. characteristic sym pic16c72 pic16cr72 units conditions min t yp? max min t yp? max d001 supply v oltage v dd 2.5 - 6.0 2.5 - 5.5 v lp , xt , rc (dc - 4 mhz) d002* ram data retention v oltage (note 1) v dr - 1.5 - - 1.5 - v d003 v dd star t v oltage to ensure inter nal p o w er- on reset signal v por - v ss - - v ss - v see section on p o w er- on reset f or details d004* v dd r ise r ate to ensure inter nal p o w er- on reset signal s vdd 0.05 - - 0.05 - - v/ms see section on p o w er- on reset f or details d005 bro wn-out reset v olt- age bvdd 3.7 4.0 4.3 3.7 4.0 4.3 v boden bit in con gur a- tion w ord enab led d010 supply current (note 2,5) i dd - 2.0 3.8 - 2.0 3.8 ma xt, rc osc con gur ation f osc = 4 mhz, v dd = 3.0v (note 4) d010a - 22.5 48 - 22.5 48 m a lp osc con gur ation f osc = 32 khz, v dd = 3.0v , wdt disab led d015* bro wn-out reset current (note 6) d ibor - 350 425 - 350 425 m a bor enab led v dd = 5.0v d020 p o w er-do wn current (note 3,5) i pd - 7.5 30 - 7.5 30 m a v dd = 3.0v , wdt enab led, -40 c to +85 c d021 - 0.9 5 - 0.9 5 m a v dd = 3.0v , wdt dis- ab led, 0 c to +70 c d021a - 0.9 5 - 0.9 5 m a v dd = 3.0v , wdt dis- ab led, -40 c to +85 c d023* bro wn-out reset current (note 6) d ibor - 350 425 - 350 425 m a bor enab led v dd = 5.0v * these par ameters are char acter iz ed b ut not tested. ? data in "t yp" column is at 5v , 25?c unless otherwise stated. these par ameters are f or design guidance only and are not tested. note 1: this is the limit to which v dd can be lo w ered without losing ram data. note 2: the supply current is mainly a function of the oper ating v oltage and frequency . other f actors such as i/o pin loading and s witching r ate , oscillator type , inter nal code e x ecution patter n, and temper ature also ha v e an impact on the current con- sumption. the test conditions f or all i dd measurements in activ e oper ation mode are: osc1 = e xter nal square w a v e , from r ail to r ail; all i/o pins tr istated, pulled to v dd mclr = v dd ; wdt enab led/disab led as speci ed. note 3: the po w er-do wn current in sleep mode does not depend on the oscillator type . p o w er-do wn current is measured with the par t in sleep mode , with all i/o pins in hi-impedance state and tied to v dd and v ss . note 4: f or rc osc con gur ation, current through re xt is not included. the current through the resistor can be estimated b y the f or m ula ir = v dd /2re xt (ma) with re xt in kohm. note 5: timer1 oscillator (when enab led) adds appro ximately 20 m a to the speci cation. this v alue is from char acter ization and is f or design guidance only . this is not tested. note 6: the d current is the additional current consumed when this per ipher al is enab led. this current should be added to the base i dd or i pd measurement.
pic16c72 series ? 1998 microchip technology inc. preliminary ds39016a -page 81 13.3 dc characteristics: pic16c72/cr72-04 (commer cial, industrial, extended ) pic16c72/cr72-10 (commer cial, industrial, extended ) pic16c72/cr72-20 (commer cial, industrial, extended ) pic16lc72/lcr72-04 (commer cial, industrial) dc chara cteristics standard oper ating conditions (unless otherwise stated) oper ating temper ature -40?c t a +125?c f or e xtended , -40?c t a +85?c f or industr ial and 0?c t a +70?c f or commercial oper ating v oltage v dd r ange as descr ibed in dc spec section 13.1 and section 13.2 . p aram no. characteristic sym min t yp? max units conditions input lo w v olta g e i/o por ts v il d030 with ttl b uff er v ss - 0.15 v dd v f or entire v dd r ange d030a vss - 0.8v v 4.5 v dd 5.5v d031 with schmitt t r igger b uff er v ss - 0.2 v dd v d032 mclr , osc1 (in rc mode) v ss - 0.2 v dd v d033 osc1 (in xt , hs and lp) v ss - 0.3 v dd v note1 input high v olta g e i/o por ts v ih - d040 with ttl b uff er 2.0 - v dd v 4.5 v dd 5.5v d040a 0. 25v dd + 0.8 v - v dd v f or entire v dd r ange d041 with schmitt t r igger b uff er 0.8 v dd - v dd v f or entire v dd r ange d042 mclr 0.8 v dd - v dd v d042a osc1 (xt , hs and lp) 0.7 v dd - vdd v note1 d043 osc1 (in rc mode) 0.9 v dd - v dd v d070 por tb weak pull-up current i purb 50 250 ?400 m a v dd = 5v , v pin = v ss input leaka g e current (notes 2, 3) d060 i/o por ts i il - - 1 m a vss v pin v dd , pin at hi- impedance d061 mclr , ra4/t0cki - - 5 m a vss v pin v dd d063 osc1 - - 5 m a vss v pin v dd , xt , hs and lp osc con gur ation output lo w v olta g e d080 i/o por ts v ol - - 0.6 v i ol = 8.5 ma, v dd = 4.5v , -40 c to +85 c d080a - - 0.6 v i ol = 7.0 ma, v dd = 4.5v , -40 c to +125 c d083 osc2/clk out (rc osc con g) - - 0.6 v i ol = 1.6 ma, v dd = 4.5v , -40 c to +85 c d083a - - 0.6 v i ol = 1.2 ma, v dd = 4.5v , -40 c to +125 c * these par ameters are char acter iz ed b ut not tested. ? data in ? yp column is at 5v , 25 c unless otherwise stated. these par ameters are f or design guidance only and are not tested. note 1: in rc oscillator con gur ation, the osc1/clkin pin is a schmitt tr igger input. it is not recommended that the pic16c7x be dr iv en with e xter nal cloc k in rc mode . note 2: the leakage current on the mclr / v pp pin is strongly dependent on the applied v oltage le v el. the speci ed le v els repre- sent nor mal oper ating conditions . higher leakage current ma y be measured at diff erent input v oltages . note 3: negativ e current is de ned as current sourced b y the pin.
pic16c72 series ds39016a -page 82 preliminary ? 1998 microchip technology inc. output high v olta g e d090 i/o por ts (note 3) v oh v dd - 0.7 - - v i oh = -3.0 ma, v dd = 4.5v , -40 c to +85 c d090a v dd - 0.7 - - v i oh = -2.5 ma, v dd = 4.5v , -40 c to +125 c d092 osc2/clk out (rc osc con g) v dd - 0.7 - - v i oh = -1.3 ma, v dd = 4.5v , -40 c to +85 c d092a v dd - 0.7 - - v i oh = -1.0 ma, v dd = 4.5v , -40 c to +125 c d150* open-drain high v olta g e v od - - 14 v ra4 pin , pic16 c 72/ lc 72 - - tbd v ra4 pin, pic16 cr 72/ lcr 72 capacitive loading specs on output pins d100 osc2 pin c osc2 - - 15 pf in xt , hs and lp modes when e xter nal cloc k is used to dr iv e osc1. d101 d102 all i/o pins and osc2 (in rc mode) scl, sd a in i 2 c mode c io cb - - - - 50 400 pf pf dc chara cteristics standard oper ating conditions (unless otherwise stated) oper ating temper ature -40?c t a +125?c f or e xtended , -40?c t a +85?c f or industr ial and 0?c t a +70?c f or commercial oper ating v oltage v dd r ange as descr ibed in dc spec section 13.1 and section 13.2 . p aram no. characteristic sym min t yp? max units conditions * these par ameters are char acter iz ed b ut not tested. ? data in ? yp column is at 5v , 25 c unless otherwise stated. these par ameters are f or design guidance only and are not tested. note 1: in rc oscillator con gur ation, the osc1/clkin pin is a schmitt tr igger input. it is not recommended that the pic16c7x be dr iv en with e xter nal cloc k in rc mode . note 2: the leakage current on the mclr / v pp pin is strongly dependent on the applied v oltage le v el. the speci ed le v els repre- sent nor mal oper ating conditions . higher leakage current ma y be measured at diff erent input v oltages . note 3: negativ e current is de ned as current sourced b y the pin.
pic16c72 series ? 1998 microchip technology inc. preliminary ds39016a -page 83 13.4 timing p arameter symbology the timing par ameter symbols ha v e been created f ol- lo wing one of the f ollo wing f or mats: figure 13-1: load conditions 1. tpps2pps 3. t cc : st (i 2 c speci cations only) 2. tpps 4. ts (i 2 c speci cations only) t f f requency t time lo w ercase letters (pp) and their meanings: pp cc ccp1 osc osc1 c k clk out rd rd cs cs rw rd or wr di sdi sc sck do sdo ss ss dt data in t0 t0cki io i/o por t t1 t1cki mc mclr wr wr uppercase letters and their meanings: s f f all p p er iod h high r rise i in v alid (hi-impedance) v v alid l lo w z hi-impedance i 2 c only aa output access high high b uf bus free lo w lo w t cc : st (i 2 c speci cations only) cc hd hold su setup st d a t d a t a input hold st o st op condition st a st ar t condition v dd /2 c l r l pin pin v ss v ss c l r l = 464 w c l = 50 pf f or all pins e xcept osc2 15 pf f or osc2 output load condition 1 load condition 2
pic16c72 series ds39016a -page 84 preliminary ? 1998 microchip technology inc. 13.5 timing dia grams and speci cations figure 13-2: external cloc k timing osc1 clk out q4 q1 q2 q3 q4 q1 1 2 3 3 4 4 t able 13-3 external cloc k timing requirements p arameter no. sym characteristic min t yp? max units conditions f osc exter nal clkin f requency (note 1) dc 4 mhz xt and rc osc mode dc 4 mhz hs osc mode (-04) dc 10 mhz hs osc mode (-10) dc 20 mhz hs osc mode (-20) dc 200 khz lp osc mode oscillator f requency (note 1) dc 4 mhz rc osc mode 0.1 4 mhz xt osc mode 4 5 20 200 mhz khz hs osc mode lp osc mode 1 t osc exter nal clkin p er iod (note 1) 250 ns xt and rc osc mode 250 ns hs osc mode (-04) 100 ns hs osc mode (-10) 50 ns hs osc mode (-20) 5 m s lp osc mode oscillator p er iod (note 1) 250 ns rc osc mode 250 10,000 ns xt osc mode 250 250 ns hs osc mode (-04) 100 50 250 250 ns ns hs osc mode (-10) hs osc mode (-20) 5 m s lp osc mode 2 t cy instr uction cycle time (note 1) 200 dc ns t cy = 4/ f osc 3 t osl, t osh exter nal cloc k in (osc1) high or lo w time 100 ns xt oscillator 2.5 m s lp oscillator 15 ns hs oscillator 4 t osr, t osf exter nal cloc k in (osc1) rise or f all time ? 25 ns xt oscillator ? 50 ns lp oscillator 15 ns hs oscillator ? data in "t yp" column is at 5v , 25?c unless otherwise stated. these par ameters are f or design guidance only and are not tested. note 1: instr uction cycle per iod ( t cy ) equals f our times the input oscillator time-base per iod. all speci ed v alues are based on char acter ization data f or that par ticular oscillator type under standard oper ating conditions with the de vice e x ecuting code . exceeding these speci ed limits ma y result in an unstab le oscillator oper ation and/or higher than e xpected current consumption. all de vices are tested to oper ate at "min." v alues with an e xter nal cloc k applied to the osc1/clkin pin. when an e xter nal cloc k input is used, the "max." cycle time limit is "dc" (no cloc k) f or all de vices .
pic16c72 series ? 1998 microchip technology inc. preliminary ds39016a -page 85 figure 13-3: clk ou t and i/o timing t able 13-4 clk out and i/o timing requirements p arameter no. sym characteristic min t yp? max units conditions 10* t osh2c kl osc1 - to clk out 75 200 ns note 1 11* t osh2c kh osc1 - to clk out - 75 200 ns note 1 12* tc kr clk out r ise time 35 100 ns note 1 13* tc kf clk out f all time 35 100 ns note 1 14* tc kl2iov clk out to p or t out v alid 0.5 t cy + 20 ns note 1 15* tiov2c kh p or t in v alid bef ore clk out - t osc + 200 ns note 1 16* tc kh2ioi p or t in hold after clk out - 0 ns note 1 17* t osh2iov osc1 - (q1 cycle) to p or t out v alid 50 150 ns 18* t osh2ioi osc1 - (q2 cycle) to p or t input in v alid (i/o in hold time) pic16 c 72 / cr 72 100 ns pic16 lc 72 / lcr 72 200 ns 19* tiov2osh p or t input v alid to osc1 - (i/o in setup time) 0 ns 20* tior p or t output r ise time pic16 c 72 / cr 72 10 40 ns pic16 lc 72 / lcr 72 80 ns 21* tiof p or t output f all time pic16 c 72 / cr 72 10 40 ns pic16 lc 72 / lcr 72 80 ns 22??* tinp int pin high or lo w time t cy ns 23??* t rbp rb7:rb4 change int high or lo w time t cy ns * these par ameters are char acter iz ed b ut not tested. ? data in "t yp" column is at 5v , 25?c unless otherwise stated. these par ameters are f or design guidance only and are not tested. ?? these par ameters are asynchronous e v ents not related to an y inter nal cloc k edges . note 1: measurements are tak en in rc mode where clk out output is 4 x t osc . note: ref er to figure 13-1 f or load conditions . osc1 clk out i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 19 18 15 11 12 16 old v alue ne w v alue
pic16c72 series ds39016a -page 86 preliminary ? 1998 microchip technology inc. figure 13-4: reset, w atc hdog timer , oscillator s tar t-up timer and p o wer -up timer timing figure 13-5: br o wn-out reset timing t able 13-5 reset, w atc hdog timer , oscillator star t-up timer , p o wer -up timer , and br o wn-out reset requirements p arameter no. sym characteristic min t yp? max units conditions 30 tmcl mclr pulse width (lo w) 2 m s v dd = 5v , -40?c to +125?c 31* t wdt w atchdog timer time-out p er iod (no prescaler) 7 18 33 ms v dd = 5v , -40?c to +125?c 32 t ost oscillation star t-up timer p er iod 1024 t osc t osc = osc1 per iod 33* tpwr t p o w er-up timer p er iod 28 72 132 ms v dd = 5v , -40?c to +125?c 34 t ioz i/o hi-impedance from mclr lo w or w atchdog timer reset 2.1 m s 35 t bor bro wn-out reset pulse width 100 m s v dd b vdd (d005) * these par ameters are char acter iz ed b ut not tested. ? data in "t yp" column is at 5v , 25?c unless otherwise stated. these par ameters are f or design guidance only and are not tested. v dd mclr inter nal por pwr t time-out osc time-out inter nal reset w atchdog timer reset 33 32 30 31 34 i/o pins 34 note: ref er to figure 13-1 f or load conditions . v dd bv dd 35
pic16c72 series ? 1998 microchip technology inc. preliminary ds39016a -page 87 figure 13-6: timer0 an d timer1 external cloc k timings t able 13-6 timer0 and timer1 external cloc k requirements p aram no. sym characteristic min t yp? max units conditions 40* tt0h t0cki high pulse width no prescaler 0.5 t cy + 20 ns must also meet par ameter 42 with prescaler 10 ns 41* tt0l t0cki lo w pulse width no prescaler 0.5 t cy + 20 ns must also meet par ameter 42 with prescaler 10 ns 42* tt0p t0cki p er iod no prescaler t cy + 40 ns with prescaler greater of: 20 or t cy + 40 n ns n = prescale v alue (2, 4, ..., 256) 45* tt1h t1cki high time synchronous , prescaler = 1 0.5 t cy + 20 ns must also meet par ameter 47 synchronous , prescaler = 2,4,8 pic16 c 7x / cr 72 15 ns pic16 lc 7x / lcr 72 25 ns asynchronous pic16 c 7x / cr 72 30 ns pic16 lc 7x / lcr 72 50 ns 46* tt1l t1cki lo w time synchronous , prescaler = 1 0.5 t cy + 20 ns must also meet par ameter 47 synchronous , prescaler = 2,4,8 pic16 c 7x / cr 72 15 ns pic16 lc 7x / lcr 72 25 ns asynchronous pic16 c 7x / cr 72 30 ns pic16 lc 7x / lcr 72 50 ns 47* tt1p t1cki input per iod synchronous pic16 c 7x / cr 72 greater of : 30 or t cy + 40 n ns n = prescale v alue (1, 2, 4, 8) pic16 lc 7x / lcr 72 greater of : 50 or t cy + 40 n n = prescale v alue (1, 2, 4, 8) asynchronous pic16 c 7x / cr 72 60 ns pic16 lc 7x / lcr 72 100 ns ft1 timer1 oscillator input frequency r ange (oscillator enab led b y setting bit t1oscen) dc ? 200 khz 48 tckeztmr1 dela y from e xter nal cloc k edge to timer increment 2t osc 7t osc * these par ameters are char acter iz ed b ut not tested. ? data in "t yp" column is at 5v , 25?c unless otherwise stated. these par ameters are f or design guidance only and are not tested. note: ref er to figure 13-1 f or load conditions . 46 47 45 48 41 42 40 ra4/t0cki rc0/t1oso/t1cki tmr0 or tmr1
pic16c72 series ds39016a -page 88 preliminary ? 1998 microchip technology inc. figure 13-7: capture/compare/pwm timin gs (ccp1) t able 13-7 capture/compare/pwm requirements (ccp1) p aram no. sym characteristic min t yp? max units conditions 50* tccl ccp1 input lo w time no prescaler 0.5 t cy + 20 ns with prescaler pic16 c 72 / cr 72 10 ns pic16 lc 72 / lcr 72 20 ns 51* tcch ccp1 input high time no prescaler 0.5 t cy + 20 ns with prescaler pic16 c 72 / cr 72 10 ns pic16 lc 72 / lcr 72 20 ns 52* tccp ccp1 input per iod 3t cy + 40 n ns n = prescale v alue (1,4 or 16) 53* tccr ccp1 output r ise time pic16 c 72 / cr 72 10 25 ns pic16 lc 72 / lcr 72 25 45 ns 54* tccf ccp1 output f all time pic16 c 72 / cr 72 10 25 ns pic16 lc 72 / lcr 72 25 45 ns * these par ameters are char acter iz ed b ut not tested. ? data in "t yp" column is at 5v , 25?c unless otherwise stated. t hese par ameters are f or design guidance only and are not tested. note: ref er to figure 13-1 f or load conditions . rc2/ccp1 (capture mode) 50 51 52 53 54 rc2/ccp1 (compare or pwm mode)
pic16c72 series ? 1998 microchip technology inc. preliminary ds39016a -page 89 figure 13-8: spi master operation timing (cke = 0) figure 13-9: spi master operation timing (cke = 1) ss sck (ckp = 0) sck (ckp = 1) sdo sdi 70 71 72 73 74 75, 76 78 79 80 79 78 msb lsb bit6 - - - - - -1 msb in lsb in bit6 - - - -1 ref er to figure 13-1 f or load conditions . ss sck (ckp = 0) sck (ckp = 1) sdo sdi 81 71 72 74 75, 76 78 80 msb 79 73 msb in bit6 - - - - - -1 lsb in bit6 - - - -1 lsb ref er to figure 13-1 f or load conditions .
pic16c72 series ds39016a -page 90 preliminary ? 1998 microchip technology inc. figure 13-10: spi sla ve mode timing (cke = 0) figure 13-11: spi sla ve mode timing (cke = 1) ss sck (ckp = 0) sck (ckp = 1) sdo sdi 70 71 72 73 74 75, 76 77 78 79 80 79 78 sdi msb lsb bit6 - - - - - -1 msb in bit6 - - - -1 lsb in 83 ref er to figure 13-1 f or load conditions . ss sck (ckp = 0) sck (ckp = 1) sdo sdi 70 71 72 8 2 sdi 74 75, 76 msb bit6 - - - - - -1 lsb 7 7 msb in bit6 - - - -1 lsb in 8 0 83 ref er to figure 13-1 f or load conditions .
pic16c72 series ? 1998 microchip technology inc. preliminary ds39016a -page 91 t able 13-8 s pi sla ve mode requirements (cke=0) - pic16c72 t able 13-9 spi mode requirements - pic16cr72 p aram no. sym characteristic min t yp? max units conditions 70 tssl2sch, tssl2scl ss to sck or sck - input t cy ns 71 tsch sck input high time (sla v e mode) t cy + 20 ns 72 tscl sck input lo w tim e ( sla v e mode) t cy + 20 ns 73 tdiv2sch, tdiv2scl setup time of sdi data input to sck edge 50 ns 74 tsch2dil, tscl2dil hold time of sdi data input to sck edge 50 ns 75 tdor sdo data output r ise time 10 25 ns 76 tdof sdo data output f all time 10 25 ns 77 tssh2doz ss - to sdo output hi-impedance 10 50 ns 78 tscr sck output r ise time (master mode) 10 25 ns 79 tscf sck output f all time (master mode) 10 25 ns 80 tsch2dov , tscl2dov sdo data output v alid after sck edge 50 ns ? data in "t yp" column is at 5v , 25?c unless otherwise stated. these par ameters are f or design guidance only and are not tested . p arameter no. sym characteristic min t yp? max units conditions 70* tssl2sch, tssl2scl ss to sck or sck - input t cy ns 71* tsch sck input high time (sla v e mode) t cy + 20 ns 72* tscl sck input lo w time (sla v e mode) t cy + 20 ns 73* tdiv2sch, tdiv2scl setup time of sdi data input to sck edge 100 ns 74* tsch2dil, tscl2dil hold time of sdi data input to sck edge 100 ns 75* tdor sdo data output r ise time 10 25 ns 76* tdof sdo data output f all time 10 25 ns 77* tssh2doz ss - to sdo output hi-impedance 10 50 ns 78* tscr sck output r ise time (master mode) 10 25 ns 79* tscf sck output f all time (master mode) 10 25 ns 80* tsch2dov , tscl2dov sdo data output v alid after sck edge 50 ns 81* tdov2sch, tdov2scl sdo data output setup to sck edge t cy ns 82* tssl2dov sdo data output v alid after ss edge 50 ns 83* tsch2ssh, tscl2ssh ss - after sck edge 1. 5t cy + 40 ns * these par ameters are ch ar acter iz ed b ut not tested. ? data in "t yp" column is at 5v , 25?c unless otherwise stated. these par ameters are f or design guidance only and are not tested.
pic16c72 series ds39016a -page 92 preliminary ? 1998 microchip technology inc. figure 13-12: i 2 c bus star t/stop bits timing t able 13-10 i 2 c bus star t/stop bits requirements p arameter no. sym characteristic min t yp max units conditions 90 t su : sta st ar t condition 100 khz mode 4700 ns only rele v ant f or repeated st ar t condition setup time 400 khz mode 600 91 t hd : sta st ar t condition 100 khz mode 4000 ns after this per iod the rst cloc k pulse is gener ated hold time 400 khz mode 600 92 t su : sto st op condition 100 khz mode 4700 ns setup time 400 khz mode 600 93 t hd : sto st op condition 100 khz mode 4000 ns hold time 400 khz mode 600 note: ref er to figure 13-1 f or load conditions 91 93 scl sd a st ar t condition st op condition 90 92
pic16c72 series ? 1998 microchip technology inc. preliminary ds39016a -page 93 figure 13-13: i 2 c bus da ta timing t able 13-11 i 2 c bus data requirements p arameter no. sym characteristic min max units conditions 100 t high cloc k high time 100 khz mode 4.0 m s de vice m ust oper ate at a mini- m um of 1.5 mhz 400 khz mode 0.6 m s de vice m ust oper ate at a mini- m um of 10 mhz ssp module 1.5 t cy 101 t low cloc k lo w time 100 khz mode 4.7 m s de vice m ust oper ate at a mini- m um of 1.5 mhz 400 khz mode 1.3 m s de vice m ust oper ate at a mini- m um of 10 mhz ssp module 1.5 t cy 102 t r sd a and scl r ise time 100 khz mode 1000 ns 400 khz mode 20 + 0.1cb 300 ns cb is speci ed to be from 10 to 400 pf 103 t f sd a and scl f all time 100 khz mode 300 ns 400 khz mode 20 + 0.1cb 300 ns cb is speci ed to be from 10 to 400 pf 90 t su : sta st ar t condition setup time 100 khz mode 4.7 m s only rele v ant f or repeated st ar t condition 400 khz mode 0.6 m s 91 t hd : sta st ar t condition hold time 100 khz mode 4.0 m s after this per iod the rst cloc k pulse is gener ated 400 khz mode 0.6 m s 106 t hd : dat data input hold time 100 khz mode 0 ns 400 khz mode 0 0.9 m s 107 t su : dat data input setup time 100 khz mode 250 ns note 2 400 khz mode 100 ns 92 t su : sto st op condition setup time 100 khz mode 4.7 m s 400 khz mode 0.6 m s 109 t aa output v alid from cloc k 100 khz mode 3500 ns note 1 400 khz mode ns 110 t buf bus free time 100 khz mode 4.7 m s time the b us m ust be free bef ore a ne w tr ansmission can star t 400 khz mode 1.3 m s cb bus capacitiv e loading 400 pf note 1: as a tr ansmitter , the de vice m ust pro vide this inter nal minim um dela y time to br idge the unde ned region (min. 300 ns) of the f alling edge of scl to a v oid unintended gener ation of st ar t or st op conditions . note 2: a f ast-mode (400 khz) i 2 c-b us de vice can be used in a standard-mode (100 khz)s i 2 c-b us system, b ut the requirement tsu;d a t 3 250 ns m ust then be met. this will automatically be the case if the de vice does not stretch the lo w per iod of the scl signal. if such a de vice does stretch the lo w per iod of the scl signal, it m ust output the ne xt data bit to the sd a line t r max.+tsu;d a t = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c b us speci cation) bef ore the scl line is released. note: ref er to figure 13-1 f or load conditions 90 91 92 100 101 103 106 107 109 109 110 102 scl sd a in sd a out
pic16c72 series ds39016a -page 94 preliminary ? 1998 microchip technology inc. t able 13-12 a/d con ver ter characteristics: pic16c72 /cr72 -04 ( commer cial, industrial, extended) pic16c72 /cr72 -10 (commer cial, industrial, extended) pic16c72 /cr72 -20 (commer cial, industrial, extended ) pic16lc72 /lcr72 -04 (commer cial, industrial) p aram no. sym characteristic min t yp? max units conditions a01 n r resolution 8 bits bit v ref = v dd = 5.12v, v ss v ain v ref a02 e abs t otal absolute error < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a03 e il integ r al linear ity error < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a04 e dl diff erential linear ity error < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a05 e fs full scale error < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a06 e off offset error < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a10 monotonicity guar anteed v ss v ain v ref a20 v ref ref erence v oltage 2.5v v dd + 0.3 v a25 v ain analog input v oltage v ss - 0.3 v ref + 0.3 v a30 z ain recommended impedance of analog v oltage source 10.0 k w a40 i ad a/d con v ersion current ( v dd ) pic16 c 72 / cr 72 180 m a a v er age current con- sumption when a/d is on. (note 1) pic16 lc 72 / lcr 72 90 m a a50 i ref v ref input current (note 2) 10 1000 10 m a m a dur ing v ain acquisition. based on diff erential of v hold to v ain to charge c hold , see section 9.1 . dur ing a/d con v ersion cycle * these par ameters are char acter iz ed b ut not tested. ? data in ? yp column is at 5v , 25 c unless otherwise stated. these par ameters are f or design guidance only and are not tested. note 1: when a/d is off , it will not consume an y current other than minor leakage current. the po w er-do wn current spec includes an y such leakage from the a/d module . note 2: v ref current is from ra3 pin or v dd pin, whiche v er is selected as ref erence input.
pic16c72 series ? 1998 microchip technology inc. preliminary ds39016a -page 95 figure 13-14: a/d con ver sio n timing t able 13-13 a/d con ver sion requirements p aram no. sym characteristic min t yp? max units conditions 130 t ad a/d cloc k per iod pic16 c 72 / lcr 72 1.6 m s t osc based, v ref 3 2.5v pic16 lc 72 / lcr 72 2.0 m s t osc based, v ref full r ange pic16 c 72 / lcr 72 2.0 4.0 6.0 m s a/d rc mode pic16 lc 72 / lcr 72 2.5 6.0 9.0 m s a/d rc mode 131 t cnv con v ersion time (not including s/h time) (note 1) 9.5 t ad 132 t acq acquisition time note 2 5* 20 m s m s the minim um time is the ampli er settling time . this ma y be used if the "ne w" input v oltage has not changed b y more than 1 lsb (i.e ., 20.0 mv @ 5.12v) from the last sampled v oltage (as stated on c hold ). 134 tgo q4 to a/d cloc k star t t osc /2 if the a/d cloc k source is selected as rc , a time of t cy is added bef ore the a/d cloc k star ts . this allo ws the sleep instr uction to be e x ecuted. 135 ts wc switching from con v er t ? sample time 1.5 t ad * these par ameters are char acter iz ed b ut not tested. ? data in ? yp column is at 5v , 25 c unless otherwise stated. these par ameters are f or design guidance only and are not tested. this speci cation ensured b y design. note 1: adres register ma y be read on the f ollo wing t cy cycle . note 2: see section 9.1 f or min conditions . 131 130 132 bsf adcon 0 , go q4 a/d clk a/d d a t a adres adif go sample old_d a t a sampling st opped done new_d a t a (t osc /2) (1) 7 6 5 4 3 2 1 0 note 1: if the a/d cloc k source is selected as rc , a time of t cy is added bef ore the a/d cloc k star ts . this allo ws the sleep instr uction to be e x ecuted. 1 t cy 13 4
pic16c72 series ds39016a -page 96 preliminary ? 1998 microchip technology inc. notes:
pic16c72 pic16c72 series ? 1998 microchip technology inc. preliminary ds39016a -page 97 14.0 dc and a c characteristics graphs and t ab les - pic16c72 the g r aphs and tab les pro vided in this section are f or design guidance and are not tested or guaranteed . in some g r aphs or tab les , the data presented are outside speci ed operating rang e (i.e ., outside speci ed v dd r ange). this is f or inf ormation onl y and de vices are guar anteed to oper ate proper ly only within the speci ed r ange . the data presented in this section is a statistical summar y of data collected on units from diff erent lots o v er a per iod of time and matr ix samples . 't ypical' represents the mean of the distr ib ution at 25 c , while 'max' or 'min' represents (mean + 3 s ) and (mean - 3 s ) respectiv ely , where s is standard de viation. figure 14-1: t ypical i pd vs. v dd (wdt disab led, rc mode) figure 14-2: maxim um i pd vs. v dd (wdt disab led, rc mode) 35 30 25 20 15 10 5 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i pd (na) v dd (v olts) i pd ( m a) v dd (v olts) 10.000 1.000 0.100 0.010 0.001 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 85 c 70 c 25 c 0 c -40 c
pic16c72 series pic16c72 ds39016a -page 98 preliminary ? 1998 microchip technology inc. figure 14-3: t ypical i pd vs. v dd @ 25 c (wdt enab led, rc mode) figure 14-4: maxim um i pd vs. v dd (wdt enab led, rc mode) figure 14-5: t ypical rc oscillator frequenc y vs. v dd figure 14-6: t ypical rc oscillator frequenc y vs. v dd figure 14-7: t ypical rc oscillator frequenc y vs. v dd 25 20 15 10 5 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i pd ( m a) v dd (v olts) 35 30 25 20 15 10 5 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i pd ( m a) v dd (v olts) -40 c 0 c 70 c 85 c 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (v olts) 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 fosc (mhz) ce xt = 22 pf , t = 25 c r = 100k r = 10k r = 5k shaded area is be y ond recommended r ange . 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (v olts) 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 fosc (mhz) ce xt = 100 pf , t = 25 c r = 100k r = 10k r = 5k r = 3.3k 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (v olts) 1000 900 800 700 600 500 400 300 200 100 0 fosc (khz) ce xt = 300 pf , t = 25 c r = 3.3k r = 5k r = 10k r = 100k data based on matr ix samples . see rst page of this section f or details .
pic16c72 pic16c72 series ? 1998 microchip technology inc. preliminary ds39016a -page 99 figure 14-8: t ypical i pd vs. v dd br o wn- out detect enab led (rc mode) figure 14-9: maxim um i pd vs. v dd br o wn-out detect enab led (85 c to -40 c, rc mode) figure 14-10: t ypical i pd vs. timer1 enab led (32 k h z , rc0/rc1 = 33 p f/33 p f , rc mode) figure 14-11: maxim um i pd vs. timer1 enab led (32 k h z , rc0/rc1 = 33 p f/33 p f , 85 c to -40 c, rc mode) the shaded region represents the b uilt-in h ysteresis of the bro wn-out reset circuitr y . 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 1400 1200 1000 800 600 400 200 0 v dd (v olts) i pd ( m a) de vice in bro wn-out de vice no t in bro wn-out reset reset the shaded region represents the b uilt-in h ysteresis of the bro wn-out reset circuitr y . 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 1400 1200 1000 800 600 400 200 0 v dd (v olts) i pd ( m a) 4.3 1600 de vice no t in bro wn-out reset de vice in bro wn-out reset 30 25 20 15 10 5 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (v olts) i pd ( m a) 30 25 20 15 10 5 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (v olts) i pd ( m a) 35 40 45 data based on matr ix samples . see rst page of this section f or details .
pic16c72 series pic16c72 ds39016a -page 100 preliminary ? 1998 microchip technology inc. figure 14-12: t ypical i dd vs. frequenc y (rc mode @ 22 p f , 25 c) figure 14-13: maxim um i dd vs. frequenc y (rc mode @ 22 p f , -40 c to 85 c) 2000 1800 1600 1400 1200 800 1000 600 400 200 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 frequenc y (mhz) i dd ( m a) shaded area is 6.0v 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v be y ond recommended r ange 2000 1800 1600 1400 1200 800 1000 600 400 200 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 frequenc y (mhz) i dd ( m a) shaded area is 6.0v 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v be y ond recommended r ange data based on matr ix samples . see rst page of this section f or details .
pic16c72 pic16c72 series ? 1998 microchip technology inc. preliminary ds39016a -page 101 figure 14-14: t ypical i dd vs. frequenc y (rc mode @ 100 p f , 25 c) figure 14-15: maxim um i dd vs. frequenc y (rc mode @ 100 p f , -40 c to 85 c) 1600 1400 1200 1000 800 600 400 200 0 0 200 400 600 800 1000 1200 1400 1600 1800 frequenc y (khz) i dd ( m a) 6.0v 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v shaded area is be y ond recommended r ange 1600 1400 1200 1000 800 600 400 200 0 0 200 400 600 800 1000 1200 1400 1600 1800 frequenc y (khz) i dd ( m a) 6.0v 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v shaded area is be y ond recommended r ange data based on matr ix samples . see rst page of this section f or details .
pic16c72 series pic16c72 ds39016a -page 102 preliminary ? 1998 microchip technology inc. figure 14-16: t ypical i dd vs. frequenc y (rc mode @ 300 p f , 25 c) figure 14-17: maxim um i dd vs. frequenc y (rc mode @ 300 p f , -40 c to 85 c) 1200 1000 800 600 400 200 0 0 100 200 300 400 500 600 700 frequenc y (khz) i dd ( m a) 6.0v 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v 1200 1000 800 600 400 200 0 0 100 200 300 400 500 600 700 frequenc y (khz) i dd ( m a) 6.0v 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v data based on matr ix samples . see rst page of this section f or details .
pic16c72 pic16c72 series ? 1998 microchip technology inc. preliminary ds39016a -page 103 figure 14-18: t ypical i dd vs . capacitance @ 500 k h z (rc mode) t able 14-1 rc oscillator frequencies figure 14-19: t ransconductance( gm ) of hs oscillator vs. v dd figure 14-20: t ransconductance( gm ) of lp oscillator vs. v dd figure 14-21: t ransconductance( gm ) of xt oscillator vs. v dd ce xt re xt a vera g e fosc @ 5v , 25 c 22 pf 5k 4.12 mhz 1.4% 10k 2.35 mhz 1.4% 100k 268 khz 1.1% 100 pf 3.3k 1.80 mhz 1.0% 5k 1.27 mhz 1.0% 10k 688 khz 1.2% 100k 77.2 khz 1.0% 300 pf 3.3k 707 khz 1.4% 5k 501 khz 1.2% 10k 269 khz 1.6% 100k 28.3 khz 1.1% the percentage v ar iation indicated here is par t to par t v ar iation due to nor mal process distr ib ution. the v ar iation indicated is 3 standard de viation from a v er age v alue f or v dd = 5v . capacitance (pf) 600 i dd ( m a) 500 400 300 200 100 0 20 pf 100 pf 300 pf 5.0v 4.0v 3.0v 4.0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 gm ( m a/v) v dd (v olts) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 max -40 c t yp 25 c min 85 c shaded area is be y ond recommended r ange 110 100 90 80 70 60 50 40 30 20 10 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 gm ( m a/v) v dd (v olts) max -40 c t yp 25 c min 85 c shaded areas are be y ond recommended r ange 1000 900 800 700 600 500 400 300 200 100 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 gm ( m a/v) v dd (v olts) max -40 c t yp 25 c min 85 c shaded areas are be y ond recommended r ange data based on matr ix samples . see rst page of this section f or details .
pic16c72 series pic16c72 ds39016a -page 104 preliminary ? 1998 microchip technology inc. figure 14-22: t ypical xt al star tup time vs. v dd (lp mode , 25 c) figure 14-23: t ypical xt al star tup time vs. v dd (hs mode , 25 c) figure 14-24: t ypical xt al star tup time vs . v dd (xt mode , 25 c) t able 14-2 capacitor selection f or cr ystal oscillator s 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (v olts) star tup time (seconds) 32 khz, 33 pf/33 pf 200 khz, 15 pf/15 pf 7 6 5 4 3 2 1 4.0 4.5 5.0 5.5 6.0 v dd (v olts) star tup time (ms) 20 mhz, 33 pf/33 pf 8 mhz, 33 pf/33 pf 8 mhz, 15 pf/15 pf 20 mhz, 15 pf/15 pf osc t ype cr ystal freq cap. rang e c1 cap. rang e c2 lp 32 khz 33 pf 33 pf 200 khz 15 pf 15 pf xt 200 khz 47-68 pf 47-68 pf 1 mhz 15 pf 15 pf 4 mhz 15 pf 15 pf hs 4 mhz 15 pf 15 pf 8 mhz 15-33 pf 15-33 pf 20 mhz 15-33 pf 15-33 pf cr ystals used 32 khz epson c-001r32.768k-a 20 ppm 200 khz std xtl 200.000khz 20 ppm 1 mhz ecs ecs-10-13-1 50 ppm 4 mhz ecs ecs-40-20-1 50 ppm 8 mhz epson ca-301 8.000m-c 30 ppm 20 mhz epson ca-301 20.000m-c 30 ppm 70 60 50 40 30 20 10 0 3.0 3.5 2.5 4.0 5.0 5.5 6.0 4.5 v dd (v olts) star tup time (ms) 200 khz, 68 pf/68 pf 200 khz, 47 pf/47 pf 1 mhz, 15 pf/15 pf 4 mhz, 15 pf/15 pf data based on matr ix samples . see rst page of this section f or details .
pic16c72 pic16c72 series ? 1998 microchip technology inc. preliminary ds39016a -page 105 figure 14-25: t ypical i dd vs. frequenc y (lp mode , 25 c) figure 14-26: maxim um i dd vs. frequenc y (lp mode , 85 c to -40 c) figure 14-27: t ypical i dd vs . frequenc y (xt mode , 25 c) figure 14-28: maxim um i dd vs . frequenc y (xt mode , -40 c to 85 c) 120 100 80 60 40 20 0 0 50 100 150 200 frequenc y (khz) i dd ( m a) 6.0v 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v 120 100 80 60 40 20 0 0 50 100 150 200 frequenc y (khz) i dd ( m a) 140 6.0v 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v 1200 1000 800 600 400 200 0 0.0 0.4 frequenc y (mhz) i dd ( m a) 1400 1600 1800 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 6.0v 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v 1200 1000 800 600 400 200 0 0.0 0.4 frequenc y (mhz) i dd ( m a) 1400 1600 1800 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 6.0v 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v data based on matr ix samples . see rst page of this section f or details .
pic16c72 series pic16c72 ds39016a -page 106 preliminary ? 1998 microchip technology inc. figure 14-29: t ypical i dd vs . frequenc y (hs mode , 25 c) figure 14-30: maxim um i dd vs . frequenc y (hs mode , -40 c to 85 c) t able 14-3 t ypical epr om erase time recommendations 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0.0 1 2 4 6 8 10 12 14 16 18 20 frequenc y (mhz) i dd (ma) 6.0v 5.5v 5.0v 4.5v 4.0v 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0.0 1 2 4 6 8 10 12 14 16 18 20 frequenc y (mhz) i dd (ma) 6.0v 5.5v 5.0v 4.5v 4.0v pr ocess t ec hnology w a velength (angstr oms) intensity ( m w/ cm2) distance fr om uv lamp (inc hes) t ypical time (1) (min utes) 57k 2537 12,000 1 15 - 20 77k 2537 12,000 1 20 90k 2537 12,000 1 40 120k 2537 12,000 1 60 note 1: if these cr iter ia are not met, the er ase times will be diff erent. note: fluorescent lights and sunlight both emit ultr a violet light at the er asure w a v elength. lea ving a uv er asab le de vice s windo w unco v ered could cause , o v er time , the de vices memor y cells to become er ased. the er a- sure time f or a uorescent light is about three y ears . while sunlight requires only about one w eek. t o pre- v ent the memor y cells from losing data an opaque label should be placed o v er the er asure windo w . data based on matr ix samples . see rst page of this section f or details .
pic16cr72 pic16c72 series ? 1998 microchip technology inc. preliminary ds39016a -page 107 15.0 dc and a c characteristics graphs and t ab les - pic16cr72 no graphs or t ables a v ailable a t this time
pic16c72 series pic16cr72 ds39016a -page 108 preliminary ? 1998 microchip technology inc. notes:
pic16c72 series ? 1998 microchip technology inc. preliminary ds39016a -page 109 16.0 p ac ka ging inf ormation 16.1 p ac ka g e marking inf ormation in the e v ent the full microchip par t n umber cannot be mar k ed on one line , it will be carr ied o v er to the ne xt line thus limiting the n umber of a v ailab le char acters f or customer speci c inf or mation. note : standard o tp mar king consists of microchip par t n umber , y ear code , w eek code , f acility code , mask re vision n umber , and assemb ly code . f or o tp mar king be y ond this , cer tain pr ice adders apply . please chec k with y our microchip sales of ce . f or qtp de vices , an y special mar king adders are included in qtp pr ice . * aabbcae xxxxxxxxxxxx xxxxxxxxxxxx 28-lead ssop 9517sbp 20i/ss025 pic16c72 example 28-lead soic xxxxxxx xxxxxxxxxxxxx aabbcde mmmmmmmmmmmmmmmm example 945/caa pic16c72-04/so xxxxxxxxx xxxxxx aabbcde 28-lead pdip (skinn y dip) mmmmmmmmmmmm aabbcde example pic16c72-04/sp example 28-lead side br az ed skinn y windo w ed xxxxxxxx xxx xxxxxxxx xxx aabbcde pic16c72/jw 9517ca t leg end: mm...m microchip par t n umber inf or mation xx...x customer speci c inf or mation* aa y ear code (last 2 digits of calendar y ear) bb w eek code (w eek of j an uar y 1 is w eek ?1? c f acility code of the plant at which w af er is man uf actured o = outside v endor c = 5 line s = 6 line h = 8 line d mask re vision n umber e assemb ly code of the plant or countr y of or igin in which par t w as assemb led
pic16c72 series ds39016a -page 110 preliminary ? 1998 microchip technology inc. 16.2 28-lead ceramic side braz ed dual in-line with windo w (300 mil) (jw) * controlling p ar ameter . n 1 2 r ov er all ro w spacing radius to radius width p ac kage length tip to seating plane base to seating plane t op of lead to seating plane t op to seating plane shoulder radius upper lead width lo w er lead width pcb ro w spacing dimension limits windo w width windo w length p ac kage width lead thic kness pitch number of pins units 0.170 a 0.130 w1 w2 0.290 d e1 eb e a2 l a1 1.430 0.345 0.255 0.285 0.135 0.015 0.107 b r c b1 n p 0.016 0.008 0.010 0.050 0.098 min millimeters 4.32 0.195 0.183 0.310 0.150 0.425 0.285 0.295 1.485 0.145 0.030 0.143 0.140 0.300 0.385 0.270 0.290 1.458 0.140 0.023 0.125 0.13 0.29 36.32 8.76 6.48 7.24 3.43 0.00 2.72 0.012 0.015 0.065 0.021 0.102 max nom 0.010 0.013 0.058 0.019 0.100 0.300 28 inches* 0.41 0.20 0.25 1.27 2.49 min 4.95 4.64 0.31 0.15 10.80 7.24 7.49 37.72 3.68 0.76 3.63 0.14 0.3 37.02 6.86 9.78 7.37 0.57 3.56 3.18 0.30 0.38 1.65 0.53 2.59 nom 28 0.47 0.32 0.25 1.46 2.54 7.62 max d w2 w1 e c e1 eb p a1 l b1 b a2 a
pic16c72 series ? 1998 microchip technology inc. preliminary ds39016a -page 111 16.3 28-lead plastic dual in-line ( 300 mil) (sp) * controlling p ar ameter . ? dimension ?1 does not include dam-bar protr usions . dam-bar protr usions shall not e xceed 0.003 (0.076 mm) per side or 0.006 (0.152 mm) more than dimension ?1. dimensions ? and ? do not include mold ash or protr usions . mold ash or protr usions shall not e xceed 0.010 (0.254 mm) per side or 0.020 (0.508 mm) more than dimensions ? or ?. 0.320 0.270 0.280 1.345 0.125 0.015 0.070 0.140 0.008 0.000 0.040 0.016 mold dr aft angle bottom mold dr aft angle t op ov er all ro w spacing radius to radius width molded p ac kage width tip to seating plane base to seating plane t op of lead to seating plane t op to seating plane upper lead width lo w er lead width pcb ro w spacing p ac kage length lead thic kness shoulder radius number of pins dimension limits pitch units e b eb e1 a a1 a2 l d a c r n b1 ? b p min min 0.295 0.288 5 5 10 0.350 0.283 10 0.380 0.295 15 15 0.090 1.365 0.130 0.020 0.150 0.010 0.005 nom inches* 28 0.053 0.019 0.100 0.300 1.385 0.135 0.025 0.110 0.160 0.012 0.010 0.065 0.022 max 7.49 7.30 7.11 8.89 7.18 5 8.13 6.86 5 10 10 15 15 9.65 7.49 34.67 3.30 0.51 2.29 3.81 0.25 0.13 1.33 0.48 2.54 7.62 millimeters 1.78 34.16 3.18 0.38 3.56 0.20 0.00 1.02 0.41 nom 2.79 35.18 3.43 0.64 4.06 0.30 0.25 max 28 1.65 0.56 n 1 2 r d e c eb b e1 a p l a1 b b1 a a2
pic16c72 series ds39016a -page 112 preliminary ? 1998 microchip technology inc. 16.4 28-lead plastic surface m ount (soic - wide , 300 mil bod y) (so) min p pitch mold dr aft angle bottom mold dr aft angle t op lo w er lead width radius center line gull wing radius shoulder radius chamf er distance outside dimension molded p ac kage width molded p ac kage length shoulder height ov er all p ac k. height lead thic kness f oot angle f oot length standoff number of pins b a b ? c f x a2 a1 a n e1 l l1 r1 r2 e d dimension limits units 1.27 0.050 8 12 12 0.017 0 0.014 0 0.019 15 15 0.011 0.015 0.016 0.005 0.005 0.020 0.407 0.296 0.706 0.008 0.058 0.099 28 0.394 0.011 0.009 0.010 0 0.005 0.005 0.010 0.292 0.700 0.004 0.048 0.093 0.419 0.012 0.020 0.021 0.010 0.010 0.029 4 8 0.299 0.712 0.011 0.068 0.104 0.36 0 0 12 12 0.42 15 15 0.48 10.33 17.93 10.01 0.23 0.25 0.28 0.13 0.13 0.25 0 7.42 0.10 1.22 2.36 17.78 10.64 0.41 4 0.27 0.38 0.13 0.13 0.50 0.53 0.30 0.51 0.25 0.25 0.74 7.51 0.19 28 2.50 1.47 18.08 7.59 0.28 2.64 1.73 nom inches* max nom millimeters min max n 1 2 r1 r2 d p b e1 e l1 l c b 45 x f a1 a a a2 * controlling p ar ameter . ? dimension ? does not include dam-bar protr usions . dam-bar protr usions shall not e xceed 0.003 (0.076 mm) per side or 0.006 (0.152 mm) more than dimension ? . dimensions ? and ? do not include mold ash or protr usions . mold ash or protr usions shall not e xceed 0.010 (0.254 mm) per side or 0.020 (0.508 mm) more than dimensions ? or ?.
pic16c72 series ? 1998 microchip technology inc. preliminary ds39016a -page 113 16.5 28-lead plastic surf ace mount (ssop - 209 mil bod y 5.30 mm) (ss) dimension limits mold dr aft angle bottom mold dr aft angle t op lo w er lead width lead thic kness radius center line gull wing radius shoulder radius outside dimension molded p ac kage width molded p ac kage length shoulder height ov er all p ac k. height number of pins f oot angle f oot length standoff pitch b a b ? e l c l1 f r1 r2 e1 a2 d a1 a n p units max nom min max nom min 10 10 0.38 0.22 0.25 0.64 0.25 0.25 7.90 5.38 10.33 0.21 1.17 1.99 0.012 0 0.010 0 5 5 10 0.015 10 0.007 0.005 0.020 0.005 0.005 0.306 0.208 0.402 0.005 0.036 0.073 0.026 0.205 0.015 0.005 0.000 0 0.005 0.005 0.301 0.396 0.002 0.026 0.068 0.212 4 0.025 0.009 0.010 8 0.010 0.010 0.311 28 0.407 0.008 0.046 0.078 0.25 0 0 5 0.32 5 5.20 0.13 0.00 0.38 0.13 0.13 7.65 0 10.07 0.05 0.66 1.73 5.29 0.51 0.18 0.13 4 0.13 0.13 7.78 10.20 0.13 0.91 1.86 0.65 28 8 inches millimeters* n 1 2 r1 r2 d p b e e1 l l1 b c f a a1 a2 a * controlling p ar ameter . ? dimension ? does not include dam-bar protr usions . dam-bar protr usions shall not e xceed 0.003 (0.076 mm) per side or 0.006 (0.152 mm) more than dimension ? . dimensions ? and ? do not include mold ash or protr usions . mold ash or protr usions shall not e xceed 0.010 (0.254 mm) per side or 0.020 (0.508 mm) more than dimensions ? or ?.
pic16c72 series ds39016a -page 114 preliminary ? 1998 microchip technology inc. notes:
pic16c72 series ? 1998 microchip technology inc. preliminary ds39016a -page 115 appendix a: what s ne w in this data sheet this is a ne w data sheet. ho w e v er , inf or mation on the pic16c72 de vice w as pre viously f ound in the pic16c7x data sheet, ds30390. inf or mation on the pic16cr72 de vice is ne w . appendix b: what s chang ed in this data sheet ne w data sheet. appendix c: de vice diff erences a tab le of the diff erences betw een the de vices descr ibed in this document is f ound belo w . diff erence pic16c72 pic16cr72 ssp module in spi mode basic ssp ssp
pic16c72 series ds39016a -page 116 preliminary ? 1998 microchip technology inc. notes:
pic16c72 series ? 1998 microchip technology inc. preliminary ds39016a -page 117 inde x a a/d adcon0 register ...................................................... 53 adcon1 register ...................................................... 54 adif bit ...................................................................... 55 analog input model block diagram ............................ 56 analog-to-digital converter ........................................ 53 block diagram ............................................................ 55 configuring analog port pins ..................................... 57 configuring the interrupt ............................................ 55 configuring the module .............................................. 55 conversion clock ....................................................... 57 conversions ............................................................... 58 converter characteristics .......................................... 94 go/ done bit ............................................................. 55 internal sampling switch (rss) impedance ............... 56 sampling requirements ............................................. 56 source impedance ..................................................... 56 using the ccp trigger ............................................... 58 absolute maximum ratings ............................................... 77 ack .............................................................................. 47 , 49 adie bit .............................................................................. 12 adif bit .............................................................................. 13 adres register ...................................................... 7 , 53 , 55 application notes an546 (using the analog-to-digital converter) ......... 53 an578 (use of the ssp module in the i 2 c multi-master environment) ......................................... 39 b bf .......................................................................... 40 , 43 , 47 block diagrams a/d ............................................................................. 55 analog input model .................................................... 56 capture ...................................................................... 34 compare .................................................................... 35 i 2 c mode .................................................................... 47 on-chip reset circuit ................................................ 62 pic16c72 .................................................................... 3 pic16cr72 .................................................................. 3 portc ...................................................................... 23 pwm .......................................................................... 36 ra3:ra0 and ra5 port pins ..................................... 19 ra4/t0cki pin ........................................................... 19 rb3:rb0 port pins .................................................... 21 rb7:rb4 port pins .................................................... 21 ssp in i 2 c mode ........................................................ 47 ssp in spi mode ................................................. 42 , 45 timer0 ........................................................................ 25 timer0/wdt prescaler .............................................. 26 timer2 ........................................................................ 31 watchdog timer ......................................................... 70 bor bit ........................................................................ 14 , 64 buffer full status bit, bf .............................................. 40 , 43 c c bit ...................................................................................... 9 capture/compare/pwm capture block diagram ................................................... 34 ccp1con register ........................................... 33 ccp1if .............................................................. 34 ccpr1 ............................................................... 34 ccpr1h:ccpr1l ............................................. 34 mode ................................................................. 34 prescaler ........................................................... 34 ccp timer resources ............................................... 33 compare block diagram ................................................... 35 mode ................................................................. 35 software interrupt mode .................................... 35 special event trigger ........................................ 35 special trigger output of ccp1 ........................ 35 special trigger output of ccp2 ........................ 35 section ....................................................................... 33 special event trigger and a/d conversions ............. 35 capture/compare/pwm (ccp) pwm block diagram ................................................. 36 pwm mode ................................................................ 36 pwm, example frequencies/resolutions ................. 37 ccp1ie bit ......................................................................... 12 ccp1if bit ......................................................................... 13 ccpr1h register ............................................................. 33 ccpr1l register .............................................................. 33 ccpxm0 bit ....................................................................... 33 ccpxm1 bit ....................................................................... 33 ccpxm2 bit ....................................................................... 33 ccpxm3 bit ....................................................................... 33 ccpxx bit .......................................................................... 33 ccpxy bit .......................................................................... 33 cke ................................................................................... 43 ckp ............................................................................. 41 , 44 clock polarity select bit, ckp ..................................... 41 , 44 code examples changing between capture prescalers .................... 34 initializing porta ..................................................... 19 initializing portb ..................................................... 21 initializing portc ..................................................... 23 code protection ........................................................... 59 , 72 configuration bits .............................................................. 59 d d/ a ............................................................................... 40 , 43 data/address bit, d/ a .................................................. 40 , 43 dc bit .................................................................................... 9 dc characteristics pic16c72 .................................................................. 79 development support ........................................................ 75 development tools ............................................................ 75 direct addressing .............................................................. 17 e electrical characteristics pic16c72 .................................................................. 77 external power-on reset circuit ....................................... 63 f fsr register ............................................................. 7 , 8 , 17 fuzzy logic dev. system ( fuzzy tech -mp) ................... 75 g gie bit ................................................................................ 68 i i/o ports porta ...................................................................... 19 portb ...................................................................... 21 portc ...................................................................... 23 section ....................................................................... 19 i 2 c addressing ................................................................. 48
pic16c72 series ds39016a -page 118 preliminary ? 1998 microchip technology inc. block diagram ............................................................ 47 i 2 c operation ............................................................. 47 master mode .............................................................. 51 mode .......................................................................... 47 mode selection .......................................................... 47 multi-master mode ..................................................... 51 reception ................................................................... 49 reception timing diagram ........................................ 49 scl and sda pins ..................................................... 47 slave mode ................................................................ 47 transmission .............................................................. 50 in-circuit serial programming ...................................... 59 , 72 indf register ................................................................ 8 , 17 indirect addressing ............................................................ 17 initialization condition for all register ................................ 65 instruction format .............................................................. 73 instruction set section ....................................................................... 73 summary table .......................................................... 74 int interrupt ....................................................................... 68 intcon register ............................................................... 11 intedg bit ................................................................... 10 , 68 internal sampling switch (rss) impedance ....................... 56 interrupts ............................................................................ 59 portb change ............................................................ 68 rb7:rb4 port change ............................................... 21 section ....................................................................... 68 tmr0 ......................................................................... 68 irp bit .................................................................................. 9 l loading of pc .................................................................... 15 m mclr ........................................................................... 61 , 64 memory data memory ............................................................... 6 program memory ......................................................... 5 program memory maps pic16c72 ............................................................ 5 pic16cr72 .......................................................... 5 register file maps pic16c72 ............................................................ 6 pic16cr72 .......................................................... 6 mpasm assembler ............................................................ 75 mpsim software simulator ................................................ 75 o opcode ............................................................................ 73 option register ............................................................... 10 osc selection .................................................................... 59 oscillator hs ........................................................................ 60 , 64 lp ......................................................................... 60 , 64 rc .............................................................................. 60 xt ........................................................................ 60 , 64 oscillator configurations .................................................... 60 output of tmr2 .................................................................. 31 p p ................................................................................... 40 , 43 packaging 28-lead ceramic w/window .................................... 110 28-lead pdip .......................................................... 111 28-lead soic .......................................................... 112 28-lead ssop ......................................................... 113 paging, program memory .................................................. 16 pcfg0 bit .......................................................................... 54 pcfg1 bit .......................................................................... 54 pcfg2 bit .......................................................................... 54 pcl register ............................................................. 7 , 8 , 15 pclath ............................................................................. 65 pclath register ...................................................... 7 , 8 , 15 pcon register ............................................................ 14 , 64 pd bit ............................................................................. 9 , 61 picdem-1 low-cost pic16/17 demo board .................... 75 picdem-2 low-cost pic16cxx demo board .................. 75 picmaster ? rt in-circuit emulator .............................. 75 picstart ? low-cost development system ................... 75 pie1 register ..................................................................... 12 pin functions mclr / vpp ................................................................... 4 osc1/clkin ............................................................... 4 osc2/clkout ........................................................... 4 ra0/an0 ...................................................................... 4 ra1/an1 ...................................................................... 4 ra2/an2 ...................................................................... 4 ra3/an3/ vref .............................................................. 4 ra4/t0cki .................................................................. 4 ra5/an4/ ss ................................................................ 4 rb0/int ....................................................................... 4 rb1 .............................................................................. 4 rb2 .............................................................................. 4 rb3 .............................................................................. 4 rb4 .............................................................................. 4 rb5 .............................................................................. 4 rb6 .............................................................................. 4 rb7 .............................................................................. 4 rc0/t1oso/t1cki ..................................................... 4 rc1/t1osi .................................................................. 4 rc2/ccp1 ................................................................... 4 rc3/sck/scl ............................................................. 4 rc4/sdi/sda .............................................................. 4 rc5/sdo ..................................................................... 4 rc6 ............................................................................. 4 rc7 ............................................................................. 4 sck ..................................................................... 42 ?? sdi ....................................................................... 42 ?? sdo ..................................................................... 42 ?? ss ........................................................................ 42 ?? vdd .............................................................................. 4 vss ............................................................................... 4 pinout descriptions pic16c72 .................................................................... 4 pic16cr72 ................................................................. 4 pir1 register .................................................................... 13 por ............................................................................. 63 , 64 oscillator start-up timer (ost) ........................... 59 , 63 power control register (pcon) ................................ 64 power-on reset (por) ........................................ 59 , 65 power-up timer (pwrt) ........................................... 59 power-up-timer (pwrt) .......................................... 63 time-out sequence ................................................... 64 to .............................................................................. 61 por bit ........................................................................ 14 , 64 port rb interrupt ................................................................ 68 porta .............................................................................. 65 porta register ............................................................ 7 , 19 portb .............................................................................. 65 portb register ............................................................ 7 , 21 portc .............................................................................. 65 portc register ............................................................ 7 , 23 power-down mode (sleep) .............................................. 71
pic16c72 series ? 1998 microchip technology inc. preliminary ds39016a -page 119 pr2 register ...................................................................... 31 prescaler, switching between timer0 and wdt ............... 26 pro mate ? universal programmer ................................ 75 program memory paging ........................................................................ 16 program memory maps pic16c72 .................................................................... 5 pic16cr72 .................................................................. 5 program verification .......................................................... 72 ps0 bit ............................................................................... 10 ps1 bit ............................................................................... 10 ps2 bit ............................................................................... 10 psa bit ............................................................................... 10 r r/ w .............................................................................. 40 , 43 r/ w bit ................................................................... 48 , 49 , 50 rbif bit ........................................................................ 21 , 68 rbpu bit ............................................................................ 10 rc oscillator ................................................................ 61 , 64 read/write bit information, r/ w .................................. 40 , 43 receive overflow detect bit, sspov ................................ 41 receive overflow indicator bit, sspov ............................. 44 register file ......................................................................... 6 registers initialization conditions .............................................. 65 maps pic16c72 ............................................................ 6 pic16cr72 .......................................................... 6 reset conditions ........................................................ 64 sspcon diagram ............................................................. 41 sspstat ................................................................... 43 diagram ............................................................. 40 section ............................................................... 40 reset ............................................................................ 59 , 61 reset conditions for special registers ............................. 64 rp0 bit ............................................................................. 6 , 9 rp1 bit ................................................................................. 9 s s ................................................................................... 40 , 43 sck .................................................................................... 42 scl .................................................................................... 47 sdi ..................................................................................... 42 sdo ................................................................................... 42 slave mode scl ............................................................................ 47 sda ............................................................................ 47 sleep ......................................................................... 59 , 61 smp ................................................................................... 43 special event trigger ......................................................... 58 special features of the cpu ............................................. 59 special function registers pic16c72 .................................................................... 7 pic16cr72 .................................................................. 7 special function registers, section .................................... 7 spi block diagram ...................................................... 42 , 45 mode .......................................................................... 42 serial clock ................................................................ 45 serial data in ............................................................. 45 serial data out .......................................................... 45 slave select ............................................................... 45 spi mode ................................................................... 45 sspcon .................................................................... 44 sspstat ................................................................... 43 spi clock edge select bit, cke ........................................ 43 spi data input sample phase select bit, smp ................. 43 spi mode ........................................................................... 42 ss ...................................................................................... 42 ssp module overview ....................................................... 39 section ....................................................................... 39 sspcon ................................................................... 44 sspstat .................................................................. 43 sspadd register ................................................................ 8 sspcon ..................................................................... 41 , 44 sspen ........................................................................ 41 , 44 sspie bit ........................................................................... 12 sspif bit ........................................................................... 13 sspm3:sspm0 ........................................................... 41 , 44 sspov .................................................................. 41 , 44 , 47 sspstat .......................................................................... 40 sspstat register ........................................................ 8 , 43 stack .................................................................................. 16 start bit, s .................................................................... 40 , 43 status register ................................................................. 9 stop bit, p .................................................................... 40 , 43 synchronous serial port (ssp) block diagram, spi mode ......................................... 42 spi mode ................................................................... 42 synchronous serial port enable bit, sspen ............... 41 , 44 synchronous serial port mode select bits, sspm3:sspm0 ........................................................... 41 , 44 synchronous serial port module ....................................... 39 synchronous serial port status register .......................... 43 t t0cs bit ............................................................................. 10 t1ckps0 bit ...................................................................... 27 t1ckps1 bit ...................................................................... 27 t1con register ................................................................ 27 t1oscen bit ..................................................................... 27 t1sync bit ........................................................................ 27 t2ckps0 bit ...................................................................... 32 t2ckps1 bit ...................................................................... 32 t2con register ................................................................ 32 t ad .................................................................................... 57 timer0 rtcc ......................................................................... 65 timers timer0 block diagram ................................................... 25 interrupt ............................................................. 26 prescaler ........................................................... 25 prescaler block diagram ................................... 26 section .............................................................. 25 switching prescaler assignment ....................... 26 t0if ................................................................... 68 tmr0 interrupt .................................................. 68 timer1 capacitor selection ........................................... 29 oscillator ........................................................... 29 resetting timer1 using a ccp trigger output .. 29 t1con .............................................................. 27 timer2 block diagram ................................................... 31 postscaler .......................................................... 31 prescaler ........................................................... 31 t2con .............................................................. 32
pic16c72 series ds39016a -page 120 preliminary ? 1998 microchip technology inc. timing diagrams a/d conversion .......................................................... 95 brown-out reset ........................................................ 86 capture/compare/pwm ............................................. 88 clkout and i/o ........................................................ 85 external clock timing ................................................ 84 i 2 c bus data .............................................................. 93 i 2 c bus start/stop bits ............................................... 92 i 2 c reception (7-bit address) .................................... 49 power-up timer ......................................................... 86 reset .......................................................................... 86 start-up timer ............................................................ 86 timer0 ........................................................................ 87 timer1 ........................................................................ 87 wake-up from sleep via interrupt .............................. 72 watchdog timer ......................................................... 86 tmr1cs bit ........................................................................ 27 tmr1h register .................................................................. 7 tmr1ie bit ......................................................................... 12 tmr1if bit ......................................................................... 13 tmr1l register ................................................................... 7 tmr1on bit ....................................................................... 27 tmr2 register ..................................................................... 7 tmr2ie bit ......................................................................... 12 tmr2if bit ......................................................................... 13 tmr2on bit ....................................................................... 32 to bit ................................................................................... 9 toutps0 bit ...................................................................... 32 toutps1 bit ...................................................................... 32 toutps2 bit ...................................................................... 32 toutps3 bit ...................................................................... 32 trisa register .............................................................. 8 , 19 trisb register .............................................................. 8 , 21 trisc register .............................................................. 8 , 23 u ua ................................................................................ 40 , 43 update address bit, ua ................................................ 40 , 43 w wake-up from sleep ........................................................ 71 watchdog timer (wdt) ................................... 59 , 61 , 64 , 70 wcol .......................................................................... 41 , 44 wdt ................................................................................... 64 block diagram ............................................................ 70 timeout ...................................................................... 65 write collision detect bit, wcol ................................. 41 , 44 z z bit ...................................................................................... 9
1998 microchip technology inc. ds39016a -page 121 pic16c72 series systems inf ormation and upgrade hot line the systems inf or mation and upg r ade line pro vides system users a listing of the latest v ersions of all of microchip's de v elopment systems softw are products . plus , this line pro vides inf or mation on ho w customers can receiv e an y currently a v ailab le upg r ade kits .the hot line numbers are: 1-800-755-2345 f or u .s . and most of canada, and 1-602-786-7302 f or the rest of the w or ld. t rademarks: the microchip name , logo , pic , picst ar t , picmaster and pr o ma te are registered tr ademar ks of microchip t echnology incor por ated in the u .s .a. and other countr ies . picmicro , fle x r om, mplab and fuzzy- lab are tr ademar ks and sqtp is a ser vice mar k of micro- chip in the u .s .a. all other tr ademar ks mentioned herein are the proper ty of their respectiv e companies . on-line suppor t microchip pro vides on-line suppor t on the microchip w or ld wide w eb (www) site . the w eb site is used b y microchip as a means to mak e les and inf or mation easily a v ailab le to customers . t o vie w the site , the user m ust ha v e access to the inter net and a w eb bro wser , such as netscape or microsoft explorer . files are also a v ailab le f or ftp do wnload from our ftp site . connecting to the micr oc hip internet w eb site the microchip w eb site is a v ailab le b y using y our f a v or ite inter net bro wser to attach to: www .micr oc hip.com the le tr ansf er site is a v ailab le b y using an ftp ser- vice to connect to: ftp://ftp.futureone .com/pub/micr oc hip the w eb site and le tr ansf er site pro vide a v ar iety of ser vices . users ma y do wnload les f or the latest de v elopment t ools , data sheets , application notes , user's guides , ar ticles and sample prog r ams . a v ar i- ety of microchip speci c b usiness inf or mation is also a v ailab le , including listings of microchip sales of ces , distr ib utors and f actor y representativ es . other data a v ailab le f or consider ation is: latest microchip press releases t echnical suppor t section with f requently ask ed questions design tips de vice err ata job p ostings microchip consultant prog r am member listing links to other useful w eb sites related to microchip products conf erences f or products , de v elopment systems , technical inf or mation and more listing of seminars and e v ents 980106
pic16c72 series ds39016a -page 122 1998 microchip technology inc. reader response it is our intention to pro vide y ou with the best documentation possib le to ensure successful use of y our microchip prod- uct. if y ou wish to pro vide y our comments on organization, clar ity , subject matter , and w a ys in which our documentation can better ser v e y ou, please f ax y our comments to the t echnical pub lications manager at (602) 786-7578. please list the f ollo wing inf or mation, and use this outline to pro vide us with y our comments about this data sheet . 1. what are the best f eatures of this document? 2. ho w does this document meet y our hardw are and softw are de v elopment needs? 3. do y ou nd the organization of this data sheet easy to f ollo w? if not, wh y? 4. what additions to the data sheet do y ou think w ould enhance the str ucture and subject? 5. what deletions from the data sheet could be made without aff ecting the o v er all usefulness? 6. is there an y incorrect or misleading inf or mation (what and where)? 7. ho w w ould y ou impro v e this document? 8. ho w w ould y ou impro v e our softw are , systems , and silicon products? t o: t echnical pub lications manager re: reader response t otal p ages sent f rom: name compan y address city / state / zip / countr y t elephone: (_______) _________ - _________ application (optional): w ould y ou lik e a reply? y n de vice: liter ature number : questions: f ax: (______) _________ - _________ ds39016a pic16c72 series
pic16c72 series ? 1998 microchip technology inc. preliminary ds39016a -page 123 pic16c72 series pr oduct identification system t o order or obtain inf or mation, e .g., on pr icing or deliv er y , ref er to the f actor y or the listed sales of ce . * jw de vices are uv er asab le and can be prog r ammed to an y de vice con gur ation. jw de vices meet the electr ical requirement of each oscillator type (including lc de vices). sales and suppor t p ar t no . -xx x /xx xxx p attern p ac ka g e t emperature rang e frequenc y rang e de vice de vice pic16c72 (1) , pic16c72t (2) pic16lc72 (1) , pic16lc72t (2) pic16cr72 (1) , pic16cr72t (2) pic16lcr72 (1) , pic16lcr72t (2) f requency range 02 = 2 mhz 04 = 4 mhz 10 = 10 mhz 20 = 20 mhz t emper ature range b (3) = 0 c to 70 c (commercial) i = -40 c to +85 c (industr ial) e = -40 c to +125 c (extended) p ac kage jw = cer amic dual in-line p ac kage with windo w so = small outline - 300 mil sp = skinn y pdip ss = shr ink samll outline p ac kage - 209 mil p atter n 3-digit p atter n code f or qtp , r om (b lank otherwise) examples: f) pic16c72 -04/p 301 = commercial temp ., pdip pac kage , 4 mhz, nor mal v dd limits , qtp patter n #301. g) pic16lc72 - 04i/so = industr ial temp ., soic pac kage , 200 khz, extended v dd limits . h) pic16cr72 - 10i/p = r om prog r am memor y , industr ial temp ., pdip pac kage , 10mhz, nor- mal v dd limits . note 1: c = cmos cr = cmos r om lc = lo w p o w er cmos lcr = r om v ersion, extended vdd r ange 2: t = in tape and reel - soic , ssop pac k- ages only . 3: b = b lank data sheets products suppor ted b y a preliminar y data sheet ma y ha v e an err ata sheet descr ibing minor oper ational diff erences and recom- mended w or karounds . t o deter mine if an err ata sheet e xists f or a par ticular de vice , please contact one of the f ollo wing: 1. y our local microchip sales of ce (see last page) 2. the microchip cor por ate liter ature center u .s . f ax: (602) 786-7277 3. the microchip s bulletin board, via y our local compuser v e n umber (compuser v e membership no t required). please specify which de vice , re vision of silicon and data sheet (include liter ature #) y ou are using. de velopment t ools f or the latest v ersion inf or mation and upg r ade kits f or microchip de v elopment t ools , please call 1-800-755-2345 or 1-602-786-7302. the latest v ersion of de v elopment t ools softw are can be do wnloaded from either our bulletin board or w or ldwide w eb site . (inf or- mation on ho w to connect to our bbs or www site can be f ound in the on-line suppor t section of this data sheet.)
? 2002 microchip technology inc. information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. no representation or warranty is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. use of microchip?s products as critical com- ponents in life support systems is not authorized except with express written approval by microchip. no licenses are con- veyed, implicitly or otherwise, under any intellectual property rights. trademarks the microchip name and logo, the microchip logo, filterlab, k ee l oq , microid, mplab, pic, picmicro, picmaster, picstart, pro mate, seeval and the embedded control solutions company are registered trademarks of microchip tech- nology incorporated in the u.s.a. and other countries. dspic, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, microport, migratable memory, mpasm, mplib, mplink, mpsim, mxdev, picc, picdem, picdem.net, rfpic, select mode and total endurance are trademarks of microchip technology incorporated in the u.s.a. serialized quick turn programming (sqtp) is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2002, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. microchip received qs-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona in july 1999. the company?s quality system processes and procedures are qs-9000 compliant for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms and microperipheral products. in addition, microchip ? s quality system for the design and manufacture of development systems is iso 9001 certified. note the following details of the code protection feature on picmicro ? mcus. the picmicro family meets the specifications contained in the microchip data sheet. microchip believes that its family of picmicro microcontrollers is one of the most secure products of its kind on the market to day, when used in the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowl - edge, require using the picmicro microcontroller in a manner outside the operating specifications contained in the data sheet. the person doing so may be engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconductor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ? unbreakable ? . code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our product. if you have any further questions about this matter, please contact the local sales office nearest to you.
? 2002 microchip technology inc. m americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: 480-792-7627 web address: http://www.microchip.com rocky mountain 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7966 fax: 480-792-7456 atlanta 500 sugar mill road, suite 200b atlanta, ga 30350 tel: 770-640-0034 fax: 770-640-0307 boston 2 lan drive, suite 120 westford, ma 01886 tel: 978-692-3848 fax: 978-692-3821 chicago 333 pierce road, suite 180 itasca, il 60143 tel: 630-285-0071 fax: 630-285-0075 dallas 4570 westgrove drive, suite 160 addison, tx 75001 tel: 972-818-7423 fax: 972-818-2924 detroit tri-atria office building 32255 northwestern highway, suite 190 farmington hills, mi 48334 tel: 248-538-2250 fax: 248-538-2260 kokomo 2767 s. albright road kokomo, indiana 46902 tel: 765-864-8360 fax: 765-864-8387 los angeles 18201 von karman, suite 1090 irvine, ca 92612 tel: 949-263-1888 fax: 949-263-1338 new york 150 motor parkway, suite 202 hauppauge, ny 11788 tel: 631-273-5305 fax: 631-273-5335 san jose microchip technology inc. 2107 north first street, suite 590 san jose, ca 95131 tel: 408-436-7950 fax: 408-436-7955 toronto 6285 northam drive, suite 108 mississauga, ontario l4v 1x5, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific australia microchip technology australia pty ltd suite 22, 41 rawson street epping 2121, nsw australia tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing microchip technology consulting (shanghai) co., ltd., beijing liaison office unit 915 bei hai wan tai bldg. no. 6 chaoyangmen beidajie beijing, 100027, no. china tel: 86-10-85282100 fax: 86-10-85282104 china - chengdu microchip technology consulting (shanghai) co., ltd., chengdu liaison office rm. 2401, 24th floor, ming xing financial tower no. 88 tidu street chengdu 610016, china tel: 86-28-6766200 fax: 86-28-6766599 china - fuzhou microchip technology consulting (shanghai) co., ltd., fuzhou liaison office unit 28f, world trade plaza no. 71 wusi road fuzhou 350001, china tel: 86-591-7503506 fax: 86-591-7503521 china - shanghai microchip technology consulting (shanghai) co., ltd. room 701, bldg. b far east international plaza no. 317 xian xia road shanghai, 200051 tel: 86-21-6275-5700 fax: 86-21-6275-5060 china - shenzhen microchip technology consulting (shanghai) co., ltd., shenzhen liaison office rm. 1315, 13/f, shenzhen kerry centre, renminnan lu shenzhen 518001, china tel: 86-755-2350361 fax: 86-755-2366086 hong kong microchip technology hongkong ltd. unit 901-6, tower 2, metroplaza 223 hing fong road kwai fong, n.t., hong kong tel: 852-2401-1200 fax: 852-2401-3431 india microchip technology inc. india liaison office divyasree chambers 1 floor, wing a (a3/a4) no. 11, o?shaugnessey road bangalore, 560 025, india tel: 91-80-2290061 fax: 91-80-2290062 japan microchip technology japan k.k. benex s-1 6f 3-18-20, shinyokohama kohoku-ku, yokohama-shi kanagawa, 222-0033, japan tel: 81-45-471- 6166 fax: 81-45-471-6122 korea microchip technology korea 168-1, youngbo bldg. 3 floor samsung-dong, kangnam-ku seoul, korea 135-882 tel: 82-2-554-7200 fax: 82-2-558-5934 singapore microchip technology singapore pte ltd. 200 middle road #07-02 prime centre singapore, 188980 tel: 65-334-8870 fax: 65-334-8850 taiwan microchip technology taiwan 11f-3, no. 207 tung hua north road taipei, 105, taiwan tel: 886-2-2717-7175 fax: 886-2-2545-0139 europe denmark microchip technology nordic aps regus business centre lautrup hoj 1-3 ballerup dk-2750 denmark tel: 45 4420 9895 fax: 45 4420 9910 france microchip technology sarl parc d?activite du moulin de massy 43 rue du saule trapu batiment a - ler etage 91300 massy, france tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany microchip technology gmbh gustav-heinemann ring 125 d-81739 munich, germany tel: 49-89-627-144 0 fax: 49-89-627-144-44 italy microchip technology srl centro direzionale colleoni palazzo taurus 1 v. le colleoni 1 20041 agrate brianza milan, italy tel: 39-039-65791-1 fax: 39-039-6899883 united kingdom arizona microchip technology ltd. 505 eskdale road winnersh triangle wokingham berkshire, england rg41 5tu tel: 44 118 921 5869 fax: 44-118 921-5820 01/18/02 w orldwide s ales and s ervice

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